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| xr82c684 features ! "# $ % %& ' % ' ( %( )** ' ( % %( % + , )(% ( -. ( ( ' % +( ' /001 /.0 1 $ )( 2 % 3( 44 )( % $ )( '( * ' %( ' ( 5" '6 ( (& "( )( 7 8 ' '6 -%# .8 ' '6 9 6 -% : # 5;# < ' <+)= <+)= % 3 ( * '( . ( -( % $ 3( (" %6 $ (( % $ > ' '6 3 , + , $ !(%& ( ? ( & . 2 + % ( % . 2 + % $ ( % 3( , * % ! ' % 0 $ % ( ( 3( 09 :( )( ' ( %'( * &% & ' ( , + 3 ' < 3 + 3 ' ,& general description 58 ( % %& ' % ' ( %( (% ' ('( % (' ( % * * & ( * " %& ' % ' ('( ' % ( %( , '6, (% %(, * % ( (' ' %% % %&% % & % ( ( ( ( 80.0@ (' ** % %( , $ % ( * ( % (' ' %% *( ( % /001 /.0 %1 * 00 .0 *( & * ' %% %# % '( & ' % ' &&( , 5<( > !! > (% * (' %( , ' 3 & # 3( (, * ' %(& 5+$- 0 ' %% ( (, * ' 3 3 ' %( # (%'6, ( @@( +< .0( +< ordering information part no. package operating temperature range 80.0@a-@@ @@ ( +< b 80.0@a .0 ( +< b 80.0@a-@@ @@ ( +< @ 09 80.0@a .0 ( +< @ 09 xr82c684 principles of operation figure 1 figure 2 % '6 (, * 3 ( , ( .0 00 %# % '( & % ( % ( % '6 (, %# ' %(%% * * 3( , c * '( '6%7 ! )% )** $ $ + ( ('( % # )# # ! ( (( , + )( 2 ; ; % ,(% ; ; % ,(% ) ; ; % ,(% ! ; ; ,(% % % ,(% , * ! ' % $ + % + '( ' < ,(' + % %% ! ' ! ' ) -( d )% )** 8! 8! 8!) 8!) 8! 8! 8!! 8!! $+ $+b $+0 $+9 + +b +0 +9 ! !b 9 e: : !=: 55: $=: $:: 8-<= 8 ,(% % ,(% % ,(% % + + $+ $+ $+ $+ + + ! $ $ $ $ $ $ $> $> -( d %'( ) ! $ ! )% ( $ (( , figure 1. block diagram of the xr82c684 in the 68 mode xr82c684 4 ; ; % ,(% ; ; % ,(% ) ; ; % ,(% ! ; ; ,(% % % ,(% , * ! ' % $ + % + '( ' < ,(' + % %% ! ' ! ' ) -( d )% )** 8! 8! 8!) 8!) 8! 8! 8!! 8!! $+ $+b $+0 $+9 + +b +0 +9 ! !b @ !: e: 5: 55 $=: $:: 8-<= 8 ,(% % ,(% % ,(% % + + $+ $+ $+ $+ + + ! $ $ $ $ $ $ $> $> -( d %'( )( 2 ) ! $ ! )% ( $ (( , figure 2. block diagram of the xr82c684 in the 88 mode $5$ $5 xr82c684 @ 68 pin plcc 44 pin plcc $+9 $+@ !: $+4 $+ $+) $+) 4 @ 9 $+0 $+! $+ $+ $5$ +9 +. +b ! ! ! !4 !@ !9 !. !b e: 5: +9 +@ +4 + 8 8-<= +4 8!) 8!) +4 + 5< > > 55 +) + 8! 8! $+b $+. 8!! 8!! $5 $=: $:: + 2:! 2:! + +! +0 8! 8! $+9 $+@ $+4 $+ 8 8-<= 8!) 8!) +4 5< > 55 +) + 8! 8! !: $+) $+ 4 @ 9 $+0 $+! ! ! ! !4 !@ !9 !. !b -e: 5: 8!! 8!! $5 $=: $:: + 2:! +! +0) 8! 8! $5$ xr82c684 9 pin description pin # 68 pin plcc pin # 44 pin plcc symbol type description > power supply pin. 5< $ mode select. /00 1 ' % ' & &( , (% ( 2:!f ' '( , (% ( > 3( % ' /.0 1 4 + 8 g .8 8 g 8 8 g 8 output port 2 (general purpose output). (% ( ' % ' *(, * '( % / %( ." " ' '61 # / ' ( 8 ' '61 @ +4 8) g 8 8) g 8 - g g !h output 3 (active low). , % , % # / ) %( " ' '61 # / ) ' ( " ' '61 # ( / -( &1 9 4 8!) transmitter serial data output (channel b). % %(, (*(' ( * ' ' (% %( *( % (% (% ( / (, 1 6( , % 3 %( (% ( # (% # 3 ' (% ( , ( ' <+)= $* " %( ' '6 (% % '(*( # 8)# %( (% % (* * %( (* ,(% * ( , , * (% ' '6 . @ 8!) $ receiver serial data input (channel b). % %(, (*(' ( * ' ' (% ' ( *( % $* " ' ( ' '6# 8)# (% % '(*( # % ( ( (% % (%( , , * (% ' '6 b 9 8-<= $ crystal output or external clock input. (% ( (% ' '( * %( * ' &% ''( , 3 ( %'( (% % $* %'( (% % # " ' '6 %(, % % ( (% ( $ * 80.0@ (' * '( &# % % % & %(, 3( * i '( % 3 ;j 0 ;j (% i( ' & ( ' &% %'( & " < ' ( ' '6 %(, 0 . 8 $ crystal input. '( * %( * ' &% %( * 8-<= $* %'( (% % # ''( % % ' ' * (% ( , (% ( % * (* " ' '6 (% % ( 8-<= ( +@ 8!h- << g output 4 (general purpose output). (% ( ' % ' *(, * '( % '( 3 / ' ( &- $ 1 ( (' * 8!h- << g +9 8!h- << g ) output 5 (general purpose output). (% ( ' ' *(, * '( % '( 3 / ' ( &- $ 1 ( (' * ) 8!h- << g ) xr82c684 . pin # 68 pin plcc description type symbol pin # 44 pin plcc +. 8!h g output 6 (general purpose output). (% ( ' ' *(, * '( % '( 3 / %( &1 ( (' * 8!h g +b 8!h g ) output 7 (general purpose output). (% ( ' ' *(, * '( % '( 3 / % ( &1 ( (' * ) 8!h g ) 4 b ! $- lsb of the eight bit bi-directional data bus. %* % 3 + 6 ' (% % ' %(%( , * ( % ! !b % (% ( % 3 ( (% / (, 1# "' ( , $= '&' ( ? @ 0 ! $- bi-directional data bus. 9 ! $- bi-directional data bus. . !4 $- bi-directional data bus. b !@ $- bi-directional data bus. 0 !9 $- bi-directional data bus. 4 !. $- bi-directional data bus. @ !b $- msb of the eight bit bi-directional data bus. %* % 3 + 6 ' (% % ' %(%( , * ( % ! !b % (% ( % 3 ( (% / (, 1# "' ( , $= '&' ( ? 9 - e .0 $ read/-write (input). $* (% ( (% (, 3 ( (% 3# + (% * ( , 5! '&' 3( $* (% ( (% 3# 3 ( (% 3# + (% * ( , e$5 '&' 3( 9 e: 00 $ write strobe (active low). / 31 (% ( 3 ( (% % / 31 3 ( % ' % * ! )% ( %% ,(% # 3( ( %* '' % (%( , , * e . $ chip select (active low). % (% ( % 3 (% (, ! %* % 3 + ( ! !b 3 (% 3 4 +9 8!h g ! output 15 (general purpose output). (% ( ' ' *(, * '( % ( # '( 3 / %( &1 ( (' * ! 8!h g ! @ +@ 8!h g output 14 (general purpose output). (% ( ' ' *(, * '( % ( '( 3 / %( &1 ( (' * 8!h g 9 +4 8!h- << g ! $- output 13 (general purpose output). (% ( ' ' *(, * '( % ( # '( 3 / ' ( &1 / $ 1 ( (' * ! 8!h- << g ! . + 8!h- << g output 12 (general purpose output). (% ( ' ' *(, * '( % ( # '( 3 / ' ( &1 / $ 1 ( (' * 8!h- << g xr82c684 b pin # 68 pin plcc description type symbol pin # 44 pin plcc b b 8!! $ receiver serial data input (channel d). % %(, (*(' ( * ' ' (% ' ( *( % $* " ' ( ' '6# 8!# (% % '(*( # % ( ( (% % (%( , , * (% ' '6 0 0 8!! transmitter serial data output (channel d). % %(, (*(' ( * ' ' (% %( *( % (% (% ( (, 6( , % 3 %( (% ( # (% # 3 ' (% ( , ( ' <+)= $* " %( ' '6 (% % '(*( # 8!# %( (% % (* * %( (* ,(% * ( , , * (% ' '6 !=: .0 data transfer acknowledge (three-state, active- low). %% % != ( ( * + % 5! e$5 ( (% & ' .0 ( & * + % i( % (% %(, * (% ( (' % ( i('6 & & ' 5! e$5 '&' $* %% % != ( , 5! ( # ( ( (' % + i % (% % $* != (% %% ( , $ '6 3 , '&' # (% ( * ( , + ' % * $> $ > ' , (% ( % $* %% % != ( , e$5 '&' # ( (% ( * ( , + # %# % ' ( % ** * (' $5 00 interrupt enable output (z mode; active high). (% ( (% & / (, 1 ; 3 # ( * * 3( , 3 ' (( % ' '% (% ( , ,, / 31 $* $5$ $ 5 $ ( (% / 31 $* $5 (% / 31 '% * $5$ ( # $5 3( ,, / (, 1 ' $5$ ( % ,, / (, 1 % (%% $ i % + $: ( (% ,, / 31 $* $5 (% / 31 '% % i % $ # $5 3( ( / 31# , $ (' ( # ( + % ( 6 /55 $ 1 4 $=: .0 ? $ interrupt acknowledge (active low). (% ( (% + k% % % ( i % (%% & (' e + %% % (% ( # ( ( (' % k% ( i % (% % (' # & " % '&' 3( ( '6 3 , $= '&' 3( % + k% ( '6 3 , %(, & '( , ' % * $ > ' ,(% $> % ! !b xr82c684 0 pin # 68 pin plcc description type symbol pin # 44 pin plcc 4 $:: interrupt request output (active low, open-drain). $: (% %% '' ' * * ' (k% %6 ( ( , ' (( % (% %(, 3( ( %% , $ (' ( 3( , ' ' (( % '%( , $ i % % (( 4 + 8! g 8 8! g 8 - g g !h output 11 (general purpose output). (% ( ' % ' *(, * '( % / ! %( 8 ' '61 8! g 8# / ! ' ( 8 ' '61 # '( 3 / -( d &1 - g g !h 44 4 2:! 4@ 2:! 49 + 8 g 8 8 g .8 8 g 8 output 10 (general purpose output). (% ( ' ' *(, * '( % / %( 8 .8 ' '61 f % / ' ( ' '61 4. @ + ! output 9 (general purpose output). (% ( ' ' *(, * '( % '( 3# ( / !# i % 1 ! 4b 9 +0 output 8 (general purpose output). (% ( ' ' *(, * '( % '( 3# ( / i % 1 40 . 8! transmitter serial data output (channel d). % %(, (*(' ( * ' ' (% %( *( % (% (% ( (, 6( , % 3 %( (% ( # (% # 3 ' (% ( , ( ' <+)= $* " %( ' '6 (% % '(*( # 8!# %( (% % (* * %( (* ,(% * ( , , * (% ' '6 4 b 8! $ receive serial data input (channel d). % %(, (*(' ( (% ' ( *( % $* " ' ( ' '6 (% % '(*( # (% % (%( , , * ' '6 @ $+9 $ input 15 (general purpose input). @ $+@ 8! g 58 $ input 14 (general purpose input). (% ( ( ' % ' *(, * '( % " ' '6 ( * ' ( * ! 8! g 58 @ $+4 8! g 58 $ input 13 (general purpose input). (% ( ( ' % ' *(, * '( % " ' '6 ( * %( * ! 8! g 58 @4 $+ 8 g 58 $ input 12 (general purpose input). (% ( ( ' % ' *(, * '( % " ' '6 ( * ' ( * 8 g 58 xr82c684 pin # 68 pin plcc description type symbol pin # 44 pin plcc @@ 0 $5$ ? $ interrupt enable input (z-mode; active high). $* (% '( (, ( (% ,(' / (, 1# (% ' * , ( , %6 $ i %% + $* (% ( (% ,(' / 31# (% ( ( ( * , ( , & $ i %% + note: if the user is operating this device in the ?68 mode? or in the ?88 i-mode,? then this pin should be tied to v cc . @9 $+ 8 g 58 $ input 11 (general purpose input). (% ( ( ' % ' *(, * '( % " ' '6 ( * %( * 8 g 58 @. $+ g 58 $ input 10 (general purpose input). (% ( ( ' ' *(, * '( % " ' '6 ( * -( d @b $+ ! $ input 9 (general purpose input). (% ( ( ' ' *(, * '( % '( 3# / ! 1 ( ! @0 4 $+0 $ input 8 (general purpose input). (% ( ( ' ' *(, * '( % '( 3# / 1 ( @ 4 9 $ msb of address input. (% ( # , 3( %% ( %# 9 % % ' ' ( ,(% % 3( ( (' ( , 3 ( ( % 3( + 9 4 @ $ address input. 9 44 4 $ address input. 9 4@ $ address input. 94 49 $ lsb of address input. 9@ 4. $+ $ input 0 (general purpose input). (% ( ' ' *(, * '( % '( 3 / 1 ( * 99 4b $+ ) $ input 1 (general purpose input). (% ( ' ' *(, * '( % '( 3 / 1 ( * ) ) 9. $+ g 58 $ input 2 (general purpose input). (% ( ' ' *(, * '( % " ' '6 ( * -( d 9b $+4 8 g 58 $ input 3 (general purpose input). (% ( ' ' *(, * '( % " ' '6 ( * %( 90 40 ! 00 read strobe (?88 mode?; active low). / 31 (% ( 3 ( (% % / 31 ' % ' % * %% ,(% # ! )% note: $* % (% ( , (% (' ( /.0 1 (% ( % ( > 9 $+@ 8 g 58 $ input 4 (general purpose input). (% ( ' ' *(, * '( % " ' '6 ( * ' ( xr82c684 pin # 68 pin plcc description type symbol pin # 44 pin plcc . $+9 8) g 58 $ input 5 (general purpose input). (% ( ' ' *(, * '( % " ' '6 ( * ) %( . $+. 8) g 58 $ input 6 (general purpose input). (% ( ' ' *(, * '( % " ' '6 ( * ) ' ( . $+b $ input 7 (general purpose input). .4 4 8! $ reveive serial data input (channel a). % %(, (*(' ( * ' ' (% ' ( *( % $* " ' ( ' '6# 8# (% % '(*( # (% % (%( , , * (% ' '6 .@ @ 8! transmitter serial data output (channel a). % %(, (*(' ( * ' ' (% %( *( % (% (% ( (, 6( , % 3 %( (% ( # (% # 3 ' (% ( , ( ' <+)= $* " %( ' '6 (% % '(*( # 8# %( (% % (* * %( (* ,(% * ( , , * (% ' '6 .9 @ + output 0 (general purpose output). (% ( ' % ' *(, * '( % '( 3# ( i % * .. @ + ) output 1 (general purpose output). (% ( ' % ' *(, * '( % '( 3# ( i % * ) ) .b @4 55 $ master reset (active high for the ?88 mode?, and active low for the ?68 mode?). %% ( , (% ( ' % * 3( , ( ,(% %7 # $ # $ # + # + # ( (( (j % $> # % % * -( %# % + +9 ( (, % # ' % * % ( ' % ( ( '( % 3( 8!# 8!)# 8!# 8!! 6( , (, .0 @@ > xr82c684 dc electrical characteristics 1, 2 test conditions: l9 # > l9> 9m %% 3(% % '(*( symbol parameter min. typ. max. unit conditions > $< $ < 3 > , 9 0 > > $; $ ;(, > , > > > $;8 $ ;(, > , 8-<= @ > > > < < 3 > , @ > $< l @ > ; ;(, > , @ > $; l @ $ $< $ < 6, 9 9 >$: l > $ $<5< ' +( < 6, 4 4 >$: l > $ 8< 8 $ < 3 >$: l $ 8< 8 $ < 3 b $ 8$; 8 $ ;(, >$: l > $ 8; 8 $ ;(, >$: l > $ << ! )% ( < 6, > l > $ ! ( < 6, > l > $ + 3 & 4 . 9 '( $ + 3 & 4 4 & notes 1 parameters are valid over the specified temperature and operating supply ranges. typical values are 25 c, v cc = 5v and typical processing parameters. 2 all voltages are referenced to ground (gnd). for testing, input signal levels are 0.4v and 2.4v with a transition time of 20ns maximum. all time measurements are referenced at input voltages of 0.8v and 2.0v as appropriate. see no tag. 3 measured operating with a 3.6864 mhz crystal and with all outputs open. 4 the minimum high time must be at least 1.5 times the x1/clk period and the minimum low time must be at least equal to the x1/clk period if either channel?s receiver is operating in external 1x clock mode. xr82c684 ac electrical characteristics 1, 2, 3 test conditions: l9 # > l9> 9m %% 3(% % '(*( symbol parameter min. typ. max. unit conditions reset timing (see figure 56 ) 5 55 + % e( % xr82c684 read and write cycle timing - 88 mode ( figure 57 ) 7 @ ( !# e < 3 % ; @ ; ( * !# e < 3 % ( !# e < 3 % ; ; ( * !# e ;(, % e !# e + % e( 9 % !! ! > ( * ! < 3 . b9 % ! ! )% ( , * ! ;(, % ! ! ( e ;(, % !; ! ; ( * e ;(, 9 % e! ;(, ( 3 % - e ( % 0# % z-mode interrupt cycle timing ( figure 58 ) !$ $5 ! & ( * $5$ % $ $= ( ! < 3 : % $; $= ; ( * ! ;(, % 5$ $5$ ( ! < 3 9 % 5! $5 ! & ( * $: < 3 % xr82c684 read, write and interrupt cycle timing -68 mode ( figure 59 , figure 60 and figure 61 ) 9 ( < 3 % ; 9 ; ( * ;(, % e - e ( < 3 % e; - e ( * ;(, % e ;(, + % e( # % ! $= ;(, * != < 3 % !! ! > ( * $= < 3 b9 % ! ! )% ( , * $= ;(, % ! ! ( < 3 % !; ! ; ( * < 3 9 % !< != < 3 * ! > ( % xr82c684 4 ac electrical characteristics 1, 2, 3 (cont?d) symbol parameter min. typ. max. unit conditions xr82c684 read, write and interrupt cycle timing -68 mode ( figure 59 , figure 60 and figure 61 ) (cont?d) !; != ;(, * $= ;(, % ! != ;(, $ ' * $= ;(, 9 % port timing - xr82c684 (figure 62) 7 + + $ ( !- < 3 % +; + $ ; ( * !- ;(, % +! + > ( * e- ;(, @ % interrupt output timing - xr82c684 ( figure 63 ) $ $: +4 +b 3 % % $ % ;(, * 7 * $ % % )(% ( $ $+ * $ %6 ( $ 4 4 % % clock timing ( figure 64 ) <= 8-<= 5" ;(, < 3 ( % <= 8-<= &% 5" i '& 4.0@ b4b ;j -( 5" '6 ;(, < 3 ( $+ % -( 5" '6 i '& b4b ;j 8 8 8 5" ;(, < 3 ( % * 8 8 8 5" i '& i '& .8 . ;j .8 8 ;j transmitter timing ( figure 65 ) 8! 8! ! & 8 5" < 3 49 % 8! ! & 8 $ 9 % xr82c684 @ ac electrical characteristics 1, 2, 3 (cont?d) symbol parameter min. typ. max. unit conditions receiver timing xr82c684 ( figure 66 ) 8 8! ! ( 8 5" ;(, @ % 8; 8! ! ; ( * 8 5" ;(, % notes 1 parameters are valid over the specified temperature and operating supply ranges. typical values are 25 c, v cc = 5v and typical processing parameters. 2 all voltages are referenced to ground (gnd). for testing, input signal levels are 0.4v and 2.4v with a transition time of 20 ns maxi- mum. all time measurements are referenced at input voltages of 0.8v and 2.0v as appropriate. see figure 50. 3 ac test conditions for outputs: cl = 50 pf, rl = 2.7 kohm to v cc . 4 if -cs is used as the strobing input, this parameter defines the minimum high time between -css. 5 consecutive write operations to the same register require at least three edges of the x1 clock between writes. 6 this specification imposes a 6 mhz maximum 68000 clock frequency if a read or write cycle follows immediately after the previous read or write cycle. a higher 68000 clock can be used if this is not the case. 7 this specification imposes a lower bound on -cs and -iack low, guaranteeing that they will be low for at least one clk period. 8 this parameter is specified only to insure that -dtack is asserted with respect to the rising edge of x1/clk as shown in the timing diagram, not to guarantee operation of the part. if the specified setup time is violated, -dtack may be asserted as shown or may be asserted one clock cycle later. 9 the minimum high time must be at least 1.5 times the x1/clk period and the minimum low time must be at least equal to the x1/clk period if either channel?s receiver is operating in external 1x clock mode. absolute maximum ratings 1 ! & > , b> , .9 9 > , % 3( % ' 2 9> nb> notes 1 stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. this is a stress rat- ing only, and functional operation of the device at these or any other conditions above those indicated in the ?electrical characteris- tics? section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. xr82c684 9 system description 80.0@ ' %(%% * * ( # * " ' ('( ' %f ' ' %(%( , * ( 3 %( ' ( 5' ' * & ( & , * ( , * ' ( *' 3( , * ' %% % 3( ( ( * ' % ( , % * ' ' ( %( & % ' * * 44 ( & , *(" ( %# * ' '6 ( * ( ' -( # * " & % ( " ." ' '6 ( , % ' * 44 (** *(" ( % ' ( ' & * ' &% ' ' ' %% 3 ( % * " ' '6 ( (& ( & , ( , % * ' ( %( * ' ' 6 % '( * % ( % ' ('( % %' % ' % ( %&% % ' ( %( i ** ( ' ( $ % ( ( ((j (%6 * ' ( ' ( ( ( ('( % % ( % * 3 ' ' ( (& ( ( ( %(%%( * (' 3 ** * ' (( , (% * # % ( , %% * % ( % 3 , % . ( ' -( 3 (' & % % % , ( , %# . ( ( % ( ( % . ( ( % ( % a. data bus buffer % ** ( % ( *' 3 ( 3( ( ' ( " % % $ (% ' & ( ' '6 3 %* % 6 ' 3 % + b. operation control block ' ,(' * ( '6 ' ( % ( , ' % * + , % %(, % ( % % '( % * ( ) '6 * '( % % % ( *' % * (' '(*(' &# ( (% % %( * ,(% %% ! ' ( ,# ! ' ( , * ' % % %# (&# ' ('( ' %# % % -( ( , /%% ,(% 1 ( ' ('( * ' % , , ( ) '6 ( ) '6 3( ' * ' % * 3( , ( %(, %# ( , 3 ( (% ( ( /.01 /00 17 68 mode 88 mode %% $ %# 9 %% $ %# @ e ! e 55 55 /.0 1 % ( ' % %* '6 3 , != 3 (' (% %% ( , 3 ( '&' % ( ( * + i % ( % ' %% != %(, ( (' % ( % ' ( , 3 ( '&' # i % (% % ( , '&' # ( ' (% % ( , ( '6 3 , '&' e ( *'( , .0 *( & ' %% # % ' *(, ( /00 1 (( &# 3( i( % , ,(' ( & ( *' .0 ( & ' %% figure 3 % % %' (' * ( , ,(' '( '( & xr82c684 . figure 3. external logic circuitry required to interface a 6800 family processor to an ?88-mode? xr82c684 device -e e 5 ' '6 ! 55 55 b.1 quart register addressing %%( , * ( ,(% % * (% % ( table 1 please note that some of the registers are ?read only? and others are ?write only?. each channel is provided with the following dedicated (addressable) registers. ,(% % ,(% % % ,(% % '6 ' ,(% % ' ( ; ( , ,(% ; %( ; ( , ,(% ; (( &# ' ( % * 3( , ,(% % % -' ' ( % $ % ,(% % o ) $ % ,(% % o ! $ %6 ,(% % o ) $ %6 ,(% % o ! %6 $ % ,(% % o ) %6 $ % ,(% % o ! $ > ' ,(% % o ) $ > ' ,(% % o ! "( ( & ,(% % o ) "( ( & ,(% % o ! *( &# % ' ( % ,(% % % * '( % % ( ' ('( # %' % % %-( % + + ,(% + + ,(% $+ $ + *(, ( ,(% $+ $ + *(, ( ,(% -( )& ,(% -( )& ,(% < -( < 3 )& ,(% < -( < 3 )& ,(% xr82c684 b read mode registers write mode registers address (hex) register name symbol register name symbol ,(% # # ,(% # # % ,(% # '6 ' ,(% # %6 $ % ,(% $ ,(% 4 " ; ( , ,(% # ; " ; ( , ,(% # ; @ $ + , ,(% $+ "( ( & ,(% 9 $ % ,(% $ $ %6 ,(% $ . -( )& ,(% -( )& ,(% b -( < 3 )& ,(% < -( < 3 )& ,(% < 0 ,(% # ) )# ) ,(% # ) )# ) % ,(% # ) ) '6 ' ,(% # ) ) 55>5! ,(% # ) ) ) " ; ( , ,(% # ) ;) " ; ( , ,(% # ) ;) $ > ' ,(% $> $ > ' ,(% $> ! $ + $+ + *(, ( ,(% + +b + 5 -( + )(% +) -( + )(% +) ,(% # ,(% # % ,(% '6 ' ,(% %6 $ % ,(% $ ,(% 4 " ; ( , ,(% ; " ; ( , ,(% ; @ $ + , ,(% $+ "( ( & ,(% 9 $ % ,(% $ $ %6 ,(% $ . -( # )& ,(% -( # )& ,(% b -( # < 3 )& ,(% < -( # < 3 )& ,(% < 0 ,(% ! !# ! ,(% ! !# ! % ,(% ! ! % ,(% ! ! 55>5! ,(% ! ! ) " ; ( , ,(% ! ;! " ; ( , ,(% ! ;! $ > ' ,(% $> $ > ' ,(% $> ! $ + $+ + *(, ( ,(% +0 +9 + 5 -( + )(% +) -( + )(% +) note: the shaded blocks are not read/write registers but are rather ?address-triggered? commands. table 1. quart port and register addressing xr82c684 0 table 1 ( (' % ' ' (% i( 3( 3 ,(% % %% '( 3( ' * % ,(% ( % (% / ,(% 1 ( ( ' (-%&% 3 55 ' ( (% / ( ( , 1 ' ,(% please note that the suffix ?n? is used at the end of many of the quart registers symbols in order to refer, generically, to any one of the four channels ; 3 # ' % * ( 3( % (* * %% * ,(% * ,(% # ( ( & * 3( , & e ( '' %% ,(% ( 3( ' ( / ( 1 ,(% ( 3 % '' % ( /55 +$:51 ' % ( 6 /55 +$:51 ' ' (%% & 3 (( , ( ( ' k% ,(% * # ,(% %# 3( ( ,( ' # % ,(' %% * % * '( % * ' & ,(% % (%'%% ( ( ( section g.3 b.2 command decoding 5' ' (% i( 3( ,(% $ , # * % ,(% % -(% %( # -(% ' ( # , 3( *'( (( , % ( % * (%' % ' ' ( ' % ( * * ' ,(% (% % 3 cra, crb, crc, crd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miscellaneous commands enable/disable receiver enable/disable transmitter 3( , " l : , l 5 " l !(% " l : ( % l : , l 5 " l !(% " l : > ( ! % * '( * 3 ( * ,(% % (% *( & % (, * 3 (% ( (% % ( (% %( - ' ( ( * ,(% (% % ( 6 % ( % * (%' % ' % table 2 *( % ' % %% '( 3( ( * ,(% % please note that the upper nibble commands 116 through b effects only the performance of command register?s channel. however, commands c and d effects system (or chip) level operation. bit 7 bit 6 bit 5 bit 4 description null command: reset mrn pointer: % % k% ( ( reset receiver: % ( (( ' ' ( % (* ; 3 % % ( ' ( (% (% $ (% * % reset transmitter: % % ( (( ' %( % (* ; 3 % ( 8! (% * ' (, reset error status: % ' ( ) 6 )# + (& 5 +5# ( , 5 5 5 5 %% (%# pb74q '(*(' &# (* 5 # * (' ' (% % /) '61 5 # (% ' 3( % * ' ( 5 $ (' % ( % ,(% $ ) '6 5 # ' ( +5# 5# 5# ) '' %# 3( ' ( * ,, ( % ,(% # ( (% ' (% (%% $* 5 # * (' ' (% % / ' 5 1# ' % * % ,(% * +5# 5# ) * ' ' ' & ' ' %(% $ / ' 5 1# % * % ( (' % (% % & ' ' (% * ; : 7 5 ( (' (% 3&% % % /) '6 5 1 ( (' # i( % (% ' % reset break change interrupt: % ' k% 6 ' , ( %% (# 3( ( ( $ % ,(% xr82c684 bit 7 description bit 4 bit 5 bit 6 start break: ' % 8! 3 %( % % 6 $* %( (% &# % * 6 & & 3 ( ( % $* %( (% '( # 6 ,( % 3 %(%%( * % ' ' % ( ; (% ' # (j# 85+ % * 6 3( ,( stop break: 8! ( 3( , (, 3( ( 3 ( ( % 8! 3( ( (, * ( ( * " ' ' # (* &# (% %( set rx brg select extend bit: % ' k% / ' ( )2 ' 5" )(1 clear rx brg select extend bit: % ' k% / ' ( )2 ' 5" )(1 set tx brg select extend bit: % ' k% / %( )2 ' 5" )(1 clear tx brg select extend bit: % ' k% / %( )2 ' 5" )(1 set standby mode (channel a): e (% ' (% ( 6 ( ,(% # 3 (% * ' * %( %# ' ( %# ' -( (( '( '(% ' ( % & 3 3 please note that this command effects the operation of the entire chip. normal operation is restored by a hardware reset or by invoking the ?set active mode? command. reset ius latch (channel b): e (% ' (% ( 6 ( ) ,(% # (% ( , ( ? # ( '% % $ (' $ ' % (%# ( # 3( '% $5 ,, / (, 1 select direct system clock (channel c): 3( , 3 55# ( ( 6( , (% ' # (% ( , ( /!(( &% '61 '(*(' &# (% % %'( ' '6 * i '& (% (( & 3 # ( ( , , ( * (( , ) '6 $* % ( /!(( &% % '61 # ' ( * * ' % 3( * * % ( table 15 table 15a $* % ( 6 % (% ' ( ,(% # (% /!(( & 1 3 6 (% * /(( , %(, 1 # % 3( ' ( %# % '(*( ( table 15 table 15a set active mode (channel a): e (% ' (% ( 6 ( ,(% # (% * & % % ( set z-mode (channel b): e (% ' (% ( 6 ( ) ,(% # (% ' (( ( ? ( (%'%%( * k% ( 3 ( ( ? # + % % section c.6.2 ( * 00 & select divided system clock (channel c): (% ' (% % * / ' !( ' &% % '6 1 ' (% ' 3( /(( & 1 3 6 ( )2 (( , %(, ** ' * (% ' (% ' & * * % ( table 15 table 15a please note that this command effects the baud rates for all four channels of the quart. reserved reserved table 2. miscellaneous commands, upper nibble of all command registers, unless otherwise specified xr82c684 $ (( ' % 3 (' ( , ' ,(% %# % ** % / %% (,, 1 /' % % ' % (% ( table 1 # / + ,(% %%( ,#1 * ( (*( & ( , /% 1 ( (% '(*(' &# % ' % 7 -( -( -( -( + )(% + )(% + )(% + )(% 5' ' (% ( 6 & ( ( , 3 (( , (% ' % ( , %%# % % '(*( ( table 1 " # -( (% ( 6 & ' * ( , %% 5 . please note that this ?read operation? will not result in placing the contents of a quart register on the data bus. the only thing that will happen, in response to this procedure is the counter/timer #1 will initiate counting. for a detailed discussion into the operation of the counter/timers, please see section d.2 . " * %% (,, ' % (% / + )(% 1 (% ' (% ( 6 & * ( , 3 ( * %% 5 . e % ( 6 % (% ' # -% (% % ( , ' ( (% /1 3( ( + + ,(% (%# 3( ( + % '(*( % # ' , % * ( %# + +b ' % * ( (( (% 3( ( + <(6 3(% # % * ( % +0 +9 ' % * ( (( (% 3( + ; ' # (* +pq ,# ( 3( ( + (% % /1# % * ' % ( , ( # +# (% 3 % ,(' /1 % i &# ' ( 6 * / + )(%1 ' % / + +( %1 ' ( (%'%%( ( ( * + %# % % section f c. interrupt control block $ ) '6 3% % & ( /$ ! ( 1 ( ( ' % '( 3# ( ( i % %(, $:# 3 (' & , %% '' ' * & * * 3( , %7 %( ; ,(% # )# # ! & ' ( ; ,(% # )# # ! & ' ( $ # )# ! 5 * ' ( ) 6 ( % # )# ! 5 * -( ' * ( -( -( , * ( ( %# $+# $+# $+# $+4# $+0# $+# $+# $+ $ ) '6 ' %(%% * 3 $ % ,(% % $ $# 3 $ %6 ,(% % $ $# 3 %6 $ % ,(% % $ $ 3 $ > ' ,(% % $> $> table 3 (%% % ,(% % ( %% '( 3( ( register description address location (in quart address space) $ $ % ,(% 9 . & $ $ % ,(% 9 . & $ $ %6 ,(% 9 . e ( & $ $ %6 ,(% 9 . e ( & $ %6 $ % ,(% . & $ %6 $ % ,(% . & $> $ > ' ,(% . $> $ > ' ,(% . table 3. listing and brief description of interrupt system registers xr82c684 % * ' * % ,(% % *( 37 c.1 interrupt status registers (isr1 and isr2) ' % * $% ( (' % %% * ( ( ' (( % $* & (% 3( ( % ,(% % ,, / (, 1# ' % ( , ' (( % (% '' ( , $ , # ' % * $ 3( ( (' ' %% # % ' % * $ i % * * # & ( % (' ( * % ,( & ( , ( % ,(% % $% %6 $ % ,(% % ( * * 3 $% % 37 isr1 register bit format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffullb txrdyb counter #1 ready delta break a rxrdy/ ffulla txrdya l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % isr2 register bit format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break d rxrdy/ ffull d txrdy d counter #2 ready delta break c rxrdy/ ffull c txrdy c l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % *( (( * ( , ( ' * % (% (% % 3 c.1.1 isr1 register - channels a and b isr1[7]: input port change of state: $* (% ( (% ,(' /1# ' , * % 3% ' $ + ( % $+ $+4 % % (' % (% ( & ( , $+ (* $pbq l $pbq (% ' 3 + % $ + *(, ( ,(% d $+ )& ( , $+# % 3( ( 7 $ + ( ' , % *( % * ( ( %# * 3( , , * ( %' (( * $+# % % section e please note that in order to enable this interrupt condition, the user must do two things: 1. write the appropriate data to the lower nibble of the auxiliary control register, acr1[3:0]. in this step, the user is specifying which of the four input pins, ip0 - ip3, should trigger an ?input port change? interrupt request. 2. write a logic ?1? to imr1[7]. isr1[6] delta break indicator - channel b: e (% ( (% % # ( ( (' % ) ' ( % ' ,( ( , * ' ( 6 ) (% ( (% ' % 3 + ( 6 % ' ) /55 )5= ;:25 $:5 +1 ' % table 2 ( * ( ( k% % % )5= ' (( # % % section g.2 isr1[5] rxrdy/ffull b - channel b receiver ready or fifo full * '( * (% ( (% % ' & , ( , )p.q $* (% ( *( (% ' *(, * '( % ' ( & ( (' 8!h)# /1 ( (% ( *( ( (' % % ' ' * (% ( ;) (% & & + (% ( (% % 3 ' ' (% %* * ' ( % (* ,(% ;) (% ' 3 + % ;) $* %( ' ' % ( ;) * ( # ( 3( % ,( * ;) (% / 1 $* (% ( (% ' *(, * '( % / $ 1 $ (' <<)# ( (% % 3 ' ' (% %* * ;) %* '% % ;) ' * (% ( (% ' 3 + % ;)f & / ( ,1 $ # xr82c684 6( , * " ' ' $* ' ' (% 3(( , ( '% ;) (% * # (% ( 3( % ,( * ( # 3 ' ' (% ( ;) note: if this bit is configured to reflect the ffullb indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in rhrb, following data reception. hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. isr1[4] txrdyb - channel b transmitter ready (% ( (% (' * 8!h )# )pq (% (# 3 % # ( (' % ;) (% & (% & '' ' ' * + ( (% ' 3 + 3 ( % 3 ' ' ;)f (% % ,( # 3 ' ' (% %* 8!h) (% % 3 %( (% ( (( & (% ' 3 %( (% (% ' % ( ;) 3 ( %( (% (% 3( %( isr1[3] counter #1 ready $ $5 # - d -( d 3( % $p4q ' * ' '&' * % %i 3 3 (' (% ( +4 ( $p4q 3( ' & ( 6( , %% (,, /+ :5 1 ' ) ( ( # ( $5 # /+ :51 ' 3( % - $ :5 # (% ( (% % 3 ' d ' % ( ' (% ' 3 ' (% % & /+ :51 ' e -( (% ( :5 # /+ :51 ' 3( % -( ( (%'%%( ( * -( % ' * ( section d isr1[2]: delta break a - channel a change in break %% ( * (% ( ( (' % ' ' ( % ' ,( ( , * * ' ( 6 ) (% ( (% ' 3 + ( 6 % ' /55 )5= ;:25 $:5 +1 ' ( * ( ( k% % % )5= ' (( # % % section g.2 isr1[1] rxrdya/ffull a - channel a receiver ready or fifo full * '( * (% ( (% % ' & , ( , p.q $* (% ( *( (% ' *(, * '( % / ' ( &1 ( (' 8!h# /1 ( (% ( *( ( (' % (% % ' ' * ( ;# (% & & + (% ( (% % 3 ' ' (% %* * ; (% ' 3 + % / %1 ; $* %( ' ' % ( ;# * 3( , ( # ( 3( % ,( * ; (% / 1 $* (% ( (% ' *(, * '( % $ ; * ( (' <<# ( (% % 3 ' ' (% %* * ; 3 & %* ' ' '% % ; ' * (% ( (% ' 3 + % ; $* ' ' (% 3(( , ( '% ; (% * # (% ( 3( % ,( # * 3( , ( # 3 ' ' (% ( ; note: if this bit is configured to reflect the ffulla indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in rhra, following data reception. hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. therefore, the user is advised to read rhra until empty. isr1[0]: channel a transmitter ready (% ( (% (' * 8!h # pq (% (# 3 % # ( (' % ; (% & (% & '' ' ' * + ( (% ' 3 + 3 ( % 3 ' ' ;f (% % ,( # 3 ' ' (% %* 8!h (% % 3 %( (% ( (( & (% ' 3 %( (% (% ' % ( ; 3 ( %( (% (% 3( %( c.1.2 isr2 register - channels c and d isr2[7]: input port change of state: $* (% ( (% ,(' /1# ' , * % 3% ' $ + ( % $+0 $+ % % (' % (% ( & ( , $+ (* $pbq l $pbq (% ' 3 + % $ + *(, ( ,(% $+ )& ( , $+# % 3( ( 7 ( (( $ + ( ' , % xr82c684 4 *( % * ( ( %# * 3( , , * ( %' (( * $+# % % section e please note that in order to enable this interrupt condition, the user must do two things: 1. write the appropriate data to the lower nibble of the auxiliary control register, acr2[3:0]. in this step, the user is specifying which of the four input pins (ip8 - ip11) should trigger an ?input port change? interrupt request. 2. write a logic ?1? to imr2[7]. isr2[6] delta break indicator - channel d: e (% ( (% % # ( ( (' % ! ' ( % ' ,( ( , * ' ( 6 ) (% ( (% ' % 3 + ( 6 % ' ! / % ) 6 , $ 1 ' % table 2 ( * ( ( k% % % 6 ' (( # % % section g.2 isr2[5] rxrdy/ffull d - channel d receiver ready or fifo full * '( * (% ( (% % ' & , ( , !p.q $* (% ( *( (% ' *(, * '( % / ' ( &1 ( (' 8!h!# /1 ( (% ( *( ( (' % % ' ' * (% ( ;) (% & & + (% ( (% % 3 ' ' (% %* * ' ( % (* ,(% ;! (% ' 3 + % ;! $* %( ' ' % ( ;! * ( # ( 3( % ,( * ;! (% / 1 $* (% ( (% ' *(, * '( % / $ 1 ( (' < ' ' (% %* * ;! %* '% % ;! ' * (% ( (% ' 3 + % ;!f & / ( ,1 $ # 6( , * " ' ' $* ' ' (% 3(( , ( '% ;! (% * # (% ( 3( % ,( * ( # 3 ' ' (% ( ;! note: if this bit is configured to reflect the ffulld indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in rhrd, following data reception. hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. isr2[4] txrdyd - channel d transmitter ready (% ( (% (' * 8!h !# !pq (% (# 3 % # ( (' % ;! (% & (% & '' ' ' * + ( (% ' 3 + 3 ( % 3 ' ' ;!f (% % ,( # 3 ' ' (% %* 8!h! (% % 3 %( (% ( (( & (% ' 3 %( (% (% ' % ( ;! 3 ( %( (% (% 3( %( isr2[3] counter # 2 ready $ $5 # -d -( d 3( % $p4q ' * ' '&' * % %i 3 3 (' (% ( + ( $p4q 3( ' & ( 6( , %% (,, / 1 ' ) ( ( # ( $5 # /+ :51 ' 3( % - $ :5 # (% ( (% % 3 ' ' % ( ' (% ' 3 ' (% % & /+ :51 ' e -( (% ( :5 # /+ :51 ' 3( % -( ( (%'%%( ( * -( ' * ( section d isr2[2]: delta break c - channel c change in break %% ( * (% ( ( (' % ' ' ( % ' ,( ( , * * ' ( 6 ) (% ( (% ' 3 + ( 6 % ' / % ) 6 , $ 1 ' ( * ( ( k% % % )5= ' (( # % % section g.2 isr2[1] rxrdya/ffull c - channel c receiver ready or fifo full * '( * (% ( (% % ' & , ( , p.q $* (% ( *( (% ' *(, * '( % / ' ( &1 ( (' 8!h# /1 ( (% ( *( ( (' % (% % ' ' * ( ;# (% & & + (% ( (% % 3 ' ' (% %* * ; (% ' 3 + % / %1 ; $* %( ' ' % ( ;# xr82c684 @ * 3( , ( # ( 3( % ,( * ; (% / 1 $* (% ( *( (% ' *(, * '( % $ ; * ( (' <<# (% ( *( (% % 3 ' ' (% %* * ; 3 & %* ' ' '% % ; ' * (% ( (% ' 3 + % ; $* ' ' (% 3(( , ( '% ; (% * # (% ( 3( % ,( # * 3( , ( # 3 ' ' (% ( ; note: if this bit is configured to reflect the ffullc indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in rhrc, following data reception. hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. therefore, the user is advised to read rhrc until empty. isr2[0]: channel c transmitter ready (% ( (% (' * 8!h # pq (% (# 3 % # ( (' % ; (% & (% & '' ' ' * + ( (% ' 3 + 3 ( % 3 ' ' ;f (% % ,( # 3 ' ' (% %* 8!h (% % 3 %( (% ( (( & (% ' 3 %( (% (% ' % ( ; 3 ( %( (% (% 3( %( c.2 interrupt mask registers (imr1 and imr2) $ %6 ,(% % ' /e ( &1 ,(% % 3 (' % % % ' ' (( % 3( '% (%% $ i % ' %% * # ( * * $ (% %% ( & % % $ ; 3 # * ' %%# )( * $ $ % 3 imr1 bit format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffullb txrdyb counter ready delta break a rxrdy/ ffulla txrdya l** l l** l l** l l** l l** l l** l l** l l** l imr2 bit format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break d rxrdy/ ffulld txrdy d counter ready delta break c rxrdy/ ffullc txrdyc l** l l** l l** l l** l l** l l** l l** l l** l $* % 3(% % ' ( ( # -% % 3 ( /1 ( 3( ( $# ' % ( , $ (( <(6 3(% # (% %6 ' ( ' (( '%( , ( # % % 3 ( /1 ( '( ' % ( , ' (( please note that the imrs are write only registers, and can therefore not be read by the processor. c.3 masked interrupt status register (misr1 and misr2) ' * $ ,(% (% %(' & % % * :!( , $ $ , $ l p$ %q p$ %q ((( * $ (' ( % & ( , $% (% (% 3( ( $% ' ,, / (, 1 ( ' % ( , ' (( % xr82c684 9 3 & & ( $ * # % # * 3( , ( , $ % ,(% # 3( 6 (%( % * f " ' / ( & (1 :! * $ $ ' % ( ' $% /e ( &1 ,(% % ' & ' %% # ' % * $% 3( % ( %&% &# * ' (( 3 % *3 i( % (% '((& ' (( ( % * $% c.4 interrupt vector registers, ivr1 and ivr2 % ,(% % & % * $ > ' , ( 3 (% ( , ( /.0 1 % ' ( % '( ? % % * /00 1 e ( ( * % %# ' % * $> (% &(' & % ( , %% * k% $ (' ( 3(% # ( $ # $ > ' , ( (% &(' & * ** ' ( e (% ( , ( $ # $>% ' % % , % -3 ( ,(% % * $>%# 3 ( (% ( , ( .0 ? (% % ( % '( . c.5 limitations of the quart interrupt structure $ ' ** & 3% % , , ( % ( % % ' ( ; ; $ ' (( %f -( & ' (( # ' , % ( ) 6 (( ' ( ; 3 # %( * /! ) 6 (( 1 )# % , ( % ' ( % %' % + (& 5 +5# ' ( 5 5# ( , 5 5 % % ** % ( (& ' *(, * % & '' ' * & * % % ' (( % * # %% % (% ( % % * /! <( 6 <& 1 ' '6( , %' %' % # % (% (% / ( 1 ' ( & * i & ( , % ,(% f ' '6( , * & j ( % (% (% % '( & '% (* % % % 5 / ' 1 p9q l c.6 servicing quart interrupts $ % ('( , 3( 80.0@ * % ( 3 ' , ( %7 /.0 1 /00 1 e( ( /00 1# ( % ('( , ' * (( ( $ ? $ ('( , * ' * % % (% (%'%% ( ( 3 c.6.1 ?68 mode? interrupt servicing .0 *( & * (' ' %% % % % ' ( ' %%( , '(*(' &# ( , ( % ('( ,# 3( % ( '6 3 , # * + # & '( , ' % * * $>% $> $> %# & + ! ( , ( # ' % * ' * $>% '( % ( &# 3 ( ( % (' ( % * ( ( , %( % * # ( ' ( ('( %# ' % * $>% '' (% 3 ( ,%7 $ (*& ( ' % i %( , ( 3 + ( '( *f ' , ' '( # ( , &# ' ( % ( $ (' ( * ( ( , , * %( , /> ' $ 1 ' %%( , / ( 1 ' %%( , (% %(, (*(' ( ( ' ((' ('( % %( , & ( % (' % $ / ( 1 ' %%( ,# '( * $ i %# (' ' %% 3( , , ' & ( (' ( ( (' '%( , ( & * (% ( , ' (% ' ' (' ' %% ' , ' ( ( % (' ( ( i( ' * % ( (' % % ( '& ( 3 (' 3 '' ( , ' ( ' %%( , % i &# ( , ( (( (j( * # % 3( ' * $>% 3( " '( % * % 3 @ , # ( ' %( & (% (% , * %# ( .0"k% "' ( ' # % * / % $ > ' 1 & '( * / 1 ( % (' ( % ' * & ( &( , ' % * $> & @ ; ' # % % 6 ' 6 % $ (' ( * ( ' (( % %% & $# % % p % * $>q @ ( + , & <(6 3(% # % % (%% $ (' ( * ( ' (( % %% & $# % p % * $>q @ ( + , & xr82c684 . 80.0@# (6 & .0 % ( % ( (' % %(, %' * ' % * ( $> * 3( , 55 ' (( (% % i &# (*# ( , $ '6 3 , '&' % " % '( + % * f / ( (( (j $ > ' 1 "' ( 3( , figure 4 % % %( ( % ( * 3 ( *' .0 ' %% * $ (' ' %( ( % mc68000 processor $+< $+< $+< != ! !b '( ! ' figure 4. simple illustration depicting the interfacing of the xr82c684 quart to a 68000 processor != $:: xr82c684 $=: ! !b $ + ( (& 5 ' figure 5 % % ( %' (' * 80.0@ (' ( *'( , .0 (' ' %% (% *(, % 3% & ( ' %%( , ( * (' ' %% - ( *' %% ' ( , '( '( & * %% % (% 0 4 (% ( ' (% '( '( ' %(%% * /$ + ( (& 5 ' :b@<@0# 3 4 <( 0 <( ! ' % :b@<40 (%'%%( % %# * % :b@<40 (' % /$= ! ' 1 (% /$- ( ' ! ' 1 $ (% *(, # % ( ( (& * @ * '( %' (( * (% '( '( * 3% $* i( % % (' * + # ( 3( %% '( 3# ( # %(, # $: e (% %(, ,, % / 31 $ + ( (& 5 ' :b@<@0 3( , ( $ + ( (& % (% ( (& + $ (% '% # $ + ( (& (% @ $+< l # $+< l # $+< l $ % % + ( (& < @ ( i %# + 3( ' '6 $ %6 (% * (% 3 ( % ,(% ( ( % ( ( (& $* % ( ( (& (% @ %%f + 3( '6 3 , ,( % (' * (% 3 ( i % $* % ( ( (& (% 9 , # k% ( i % 3( % (' ( ' ( * (, ( (& ( % ' (' ' %% '( % % (' (% (' ( i %# ( 3( % & %% ( , * '( % l # l # l # ( ( (' (% " % '&' 3( $ '6 3 , &' (( &# 3 .0 + (% ( # ( 3( %% )(% # # 4 # $ + ( (& # 3 ( ( ( , %% (% @ 4 % ,(' * # + 3( '6 3 , (% ( i % & % ( , l# l# 4 l # @ 4 l ' * '( % % # ::! , b@< 3( %% * ( % * / $= ! ' 1 (( &# %% 3( % %% ( % " % '&' ' ( (% %% # ( * $= ! ' 3( % %% e 3 ( % %% # $= ! ' 3( %% / $=@# & %% ( , $= ( * $ 3( $=@ %(, ( , %% # %% (%# 0 4 # , %% ' % 3 ; 3 # (* * % %% (% ,(' /1 # /$- ( ' ! ' 1 3( % $ (% *(, # xr82c684 b 3( %% # & %% ( , ( * please note that the quart does not requires that its -cs input be asserted in order to respond to an ?interrupt acknowledge? cycle. the quart only requires that its -iack input be asserted. $ % % %% ( * $= ( # 3( ' ' % * * $>% $ > ' ,(% % % ! !b# 3 ( ' & + ' % ' ' % * ( $> %# ( 3( %% != ( ( * + (% & * % + 3( " ' (% / 1 ( (' 3( & '&' ' (% / 1 '&' (% ' # + 3( , & ,( , $= ( * f 3( # ( # , != + ' != % , $ &' (% ' # " % 3 ( '&' % 3( (6 & (' % ('( , ( $* % & ( (( (j $>%# 3( % ,( , 3 .@ @ . 99 . # + 3( ( & (% & @# ( ( '( # ( &# * $ (' ( * 3 % (% %% '( 3( ( + , * + + 3( ' , ' (% '( ( % &# % % % ( ( % (' ( "(%% '( ( %&% & $* % % *( ( (( (j $>%# ( ' % 3( & * . .0 80.0@ (' # (6 & .0 % ( % ( % %(, * * ( $ > ' ,(% % . $*# ( , $ &' # + % * * $>%# + 3( ( & (% & @# 3( ' , ' / ( (( (j $ > ' 1 "' ( % (' ( # ' 4 . ( & e + % & % (' ( ' (( % '%( , ( i %% * (( # $: * 3( , sn74ls148 sn74ls138 sn74ls138 -e != ! !b xr82c684 $: $= -e != ! !b mc68000 $+< $+< $+< $ $ $4 $9 $. $b $@ b . @ 4 4 74ls10 0 4 b . 9 @ 4 $=b $=. $=9 $=@ $=4 $= $= : 4 @ 4 @ 4 %% ! ' ( , ( '( & %% ! ' ( , ( '( & $ . b 0 4 4 @ 4 b 9 @ 9 @9 b 4 @ 9 $= ! ' $- ( ' ! ' >'' 9 9 figure 5. detailed schematics of the xr82c684 interfacing to the mc68000 processor $ + ( (& 5 ' xr82c684 0 $: != $= ! !b $+< $+< 4 @ 4 > ' figure 6. xr82c684/68000 cpu interrupt cycle timing figure 6 % % (( , (, ('( , % i ' * % 3( '' -+ ( *' # ( , $ '6 3 , )% &' interrupt service routine c '( % * $ (' ( i('6 &7 $ (*& ' (( '%( , $ i % (' ( & (( ( , ' (( '%( , $ $ ( (*& '% * $ # + % ( $ % ,(% %6 $ % ,(% * ' % * ' * $% ( (*( % ' (( % '%( , $ i % section c.1 *( % ( * * $% (%'%% % 3 ' ' * (% 3( ( $% c.6.2 ?88 mode? interrupt servicing 00-$ 00-? $ % (% (' & * % /$ 1 <(6 3(% # ? % * % /?( ,1 e (% ( , ( ? # 3( ' 0 ( /( ' 1 %# + # ( , /$ '6 3 , 1 $= '&' + 3( (% ( ' * ! )%# ( * $ > ' '( * ( ( % (' ( # ( %&% & (( &# ? ,( % % 3 ' ( ((j ( i %% , % ( (' % (% (% (%'%% ( , ( ( section c.6.2.2 e (% ( , ( 00 $ # 3( ( & ( ' ( * ( + # ( , $= '&' $ > ' ( * ( # & % , ' ( $ (' ( # (% '' (% " 3( ( $ * 3( , 3 3 % % % ( 6 / ? 1 ' # ( ' ( ? , $ % * % /$ 1 # ? % /?( ,1 f (% % % % & ( ? 3 ( *'( , ?( , (' ' %% # ( $ 3 ( *'( , $ (' ' %% xr82c684 ((%( 3 $ ? (% ' %% & , /' 1 ( % $* & ( *'( , * 3( , (' ' %% %-(' ' %# % ( $ 09 00 + 009 + .0; ? 0 + $ % ; 3 # % ( , ( ? 3 ( *'( , * 3( , (' ' %% % (' ' % 000 + 00. + 00. 0@0. +% + ( + ? 0 + $ % " * 3 % '( % 3( ( ( (%'%%( % * -(' ' %% ( *'( , ( ' %%( , ' * ( (' ' %% % (% (%'%%( # ( %' (( * $ $ ' %%( , ? $ ' %%( , 3( , c.6.2.1 i-mode interrupt servicing 3( ( $ * 3( , 3 * $# 3 % $ , # + ( *'( , ( , ( $ # 3( * '( % * 3%# ( , ( % ('( , $* i( % ( % (' * + # ( 3( %% % $: ( + ' + % ' ( i %# ( 3( ( '( * ( ( % (' ( # 3( ' , ' '( + 3( '' (% * (% 3( (( , /$ '6 3 , 1 %(, ( , % ('( (% ( * ( * ' + % (( '% % * k% ( i %# 3( , (% $: ( + 3( "( / 1 ( % (' ( 3( % ' %%( , $ , 3 ' % + % ' & % ' ( ( % (' ( # 3 ( *' 3( $ !( ' $ + ' %%( , 5" > ' $ + ' %%( , direct interrupt processing $* + &% /!( ' $ + ' %%( ,1 ' + % ' ( i %# % ' (% ' ( % '( # + 3( ' , ' % '(*(' '( ( %&% & + % & ( ' ( %# (% / '( 1 (% *(" & + '( '( & (% * " # (* $: ( i % ( ( # * 09 # (% %% # + 3( ' , ' '( 4 . ( %&% & (% '( (% *(" & '( '( %(, * 09 ' ' , & % (external) vectored interrupt processing + % & (% * * ( ' %%( , &(' & $ '6 3 , ( (% /$=1 / $:1 3( % , /( ' 1 ( * ( ! )%# ( " 3 /5" 1 (% % %' ( (% * * ' ( ' %%( ,f '% '( * ( % (' ( (% ( & 3 / " 1 % + %# %' % 00 009 +# (% /( ' 1 ( * ( (% & ' * << ( % '( % '( /5 % ( 1 '( * (% /5 % ( 1 (% *(" & + '( '( %(, $* % &% (% ' * ( ' %%( ,# -% (% % %( * ( % ( , ( ( % (' ( # ' (( ' ( % '( ( % (' ( %( % (% '( ( & 5' * % $ + ' %%( , ' (i % 3( % ( , ( ( * 3( , % '( % $ % &# % ( , ( $ # 3 ( *' +- % ( table 4 table 4 % % % & * ( ' %%( , (% & & ' * % +%- % comments on 88 i-mode interrupt service routines ( , ( 00 $ ( % % % (% , ( ( ' %%( ,# 3 ' 3( .0 00 ? ) .0 00 ? % 3( ( + 3( ' % * ( $> $> ! %# ( , $= '&' (% * 3% /% ' 1 * '% % * ( i % 3 * * ' # $> (% ' ! )% (* '% * ( i % (% %% & $ ,(% $> (% ' xr82c684 4 ! )% (* '% * ( i % (% %% & $ ,(% ; ' # + ( *' .0 ? & % * $% % * $ (' ( ; 3 # + ( *' 00 $ & $%# ( , % ' * '% * ( i %# % * ( % (' ( (% ' ( % % ( ' % ( '& * % ('( , $ p /c type of interrupt processing comments 09 !( ' 09 % 3 " $ i % ( %7 $: $: 00+ 5" > ' 00 + 3( 3 % * 0 (** ' % * /<<1 ( % ' ( % $ (' ( % 00 + 3( ( '6 3 , # $:# 3 (' ' % /, 1 /<<1 ( % '( % ! )% 009 + !( ' 5" > ' 009 + % /!( '1 " $ i % ( %7 b9# .9# 99 (( &# (% + % "' % / ' 1 ( % % % 00 + .0; !( ' .0; % %( , /%6 1 " $ i % ( f $ ? 0 + $ 5" > ' ? 0 + % % "' % ' % % * 00 + ? 0 + $ !( ' $ ? 0 3( ' 40; ( %&% & (* $: ( i % ( (% %% table 4. summary of p/ c and their types of interrupt processing (i - mode) ( * ( % ( table 4 (% (%'%% ( ( ( * 3( , % '( % c.6.2.2 8051 microcontroller 09 *( & * (' ' % (% *' & $ ' % 3( ( & * (( % * % (( % ( ' 7 ' ( % ( * 0 ( $- + +4 3 . ( ( % @6 & % * 0 & % * xr82c684 4 $ ,(% % 0 & % 04-09 0 & % = 04-04 @= 09 0= 09 ( 04-09 ( ( + )% $- + % ( + 8! 8! + + +4 ( + ( ( ( 04-09 $: $: %'( 58 5 <5 +5: + figure 7. block diagram of the 8051 microcontroller + + + +4 +@ +9 +. +b +4 8! +4 8! +4 $: +44 $: +4@ +49 +4. e +4b ! 8< 8< > + 0 + + +4 +@ +9 4 +. @ +b 9 +5: <5 5 +b !b +. !. +9 !9 +@ !@ +4 !4 + ! + ! + ! > 9 . b 0 . 9 @ 4 4 @ 9 . b 0 @ 4 40 4b 4. 49 4@ 44 4 4 4 @ 4 0 b figure 8. pin out of the 8051 microcontroller 09 ' %(%% * @ 0 ( $- % * % % * '( %# % 3( (%'%% 3 port 0 (p0.0 - p0.7) (% (% % ( % 4 4 * 09 $ $ ( ( ' %(, %# ( (% % % , % $- , %(, % 3( " &# ( ' % ( " %% % ! !b port 1 (p1.0 - p1.7) + (% (' $- ( % 0 ( %# %(, % +# +# +# # ( * ( *'( , % i( : ( * '( % %%(, * + ( %f % & % % & * ( *'( , " (' % 5"' ( % 04-09 $%# 3 (' % + + ( % $- ( % % " ( % ( ( xr82c684 4 port 2 (p2.0 - p2.7) + +( % 0 (% % ' * '( % , % $-# % (, & * %% % * %(, % 3( " ' & * 9. & % * " & 0 9 port 3: + 4 (% % ( % b $ (( * '( ( , % , % $-# % ( % ( * '( % 5' * % ( % % # % (% ( table 5 # 37 bit name alternate function +4 8! ' ( ! * ( + +4 8! %( ! * ( + +4 $: 5" $ +44 $: 5" $ +4@ ( - 5" $ +49 ( - 5" $ +4. e 5" ! & e ( +4b ! 5" ! & table 5. alternate functions of port 3 pins 09 % % % (( ( % 3 (' ( *'( , 80.0@ ( % % ( % 7 ale - address latch enable $* + (% % ( (% % % 3 & * %% % <5 (% %(, ' % %% ( " ,(% ( , *( % * * & '&' ' (% (% # + ( % ( * ( ( , % ' * * & '&' # 3 %* 6 % ' -int0 (p3.2) and -int1 (p3.3) $: $: " ( i % ( % 09 5' * % ( ( % % /( ' ( 1 ' %%( , $ (% '% # /( '1 % (* * % ( % %% # , ' 3( (' & ' % '(*(' *(" '( ( ' & (% '( (% ( & '( '( %(, * 09 $ ' ' , table 6 % % '( ( ' & , ' 3( ' # (* ( * % ( % %% interrupt location $: 4; $: 4; table 6. interrupt service routine locations (in code memory) for -int0 and -int1 * # (* % (% %( , ( * % ( % % ( i % ( # % % ( % ( ( % (' ( ' (( ' ( % '( ( % (' ( (% ' * % %% '( % $* 09 (% i( ( *' " ' % ( & %' * %(j % , 9. & %# + % + % % % %% ( % + 3( * '( % ( " %%- % ! ( , *( % * * & '&' # + 3( % 3 %% & ! ( , % ' * * & '&' + 3( % ( ( '( % + 3( % % %% & <5 % * b@<4b4 % ' (' ' % ( " %% ! % %(, % figure 9 (% %' (' ( % ( , 3 80.0@ ' ( *' 09 xr82c684 44 $: ! e <5 + ! !b + 0 9 $: ! e ! !b @ 74hc373 2 ! %% ! ' ( , < ,(' 8051 cpu xr82c684 00 g $% @ 9 b figure 9. an approach to interfacing the xr82c684 quart to the 8051 microcontroller '( '( & % figure 9 3 * '( % * 3% ( , i % ( (' i %% ( * + & %% ( , (% '( 3 $: ( (% 3( '% $: ( ( + , 3 e (% % 09 + 3( *( (% " '( , (% ' ( % '( # 3( ' , ' ( % (' ( $ '% * figure 5 # %( ' k% $: ( (% ( $: ( * # ,( ( , * ( % (' ( 3( ' ( 4; ( ' & 09 + % (%% $ '6 3 , %(, '6 $ 3( c% ,( ' %%( , , k% ( % (' ( ' + % (( '% % * ( i %# k% $: ( 3( , , / (, 1 + 3( * ( % (' ( % ( c.6.2.3 8080a microprocessor 00 (' ' %% (% * ( %( * $ ' %% % $ , # ( (% 0 ( (' ' %% i( % 9># 9># > 3 % ( % (( &# (% (' ' %% i( % 3 ' (%# ( ' /' 1 + &(' &# % (' % 3 0@ '6 2 00 &% 0@ '6 2 (% % %( * ' (( ( , , ( , ' %% & (( , % ' * 00 + # * " ' &% 00 &% (% % %( * ** ( , ( ( '( ! )% (( &# %( ' 00 + (' % ( ' & ( ' % %(, %# 00 ! (' (% % %( * % ( , %(, ( , ( * ( # * 00 (' # ( * 3( , )% %(, %f ( '' %% & ( (' % $: $ '6 3 , 5 & 5e & e ( $ $ + $e + e ( xr82c684 4@ figure 10 % % %' (' * 00 + 5$: $: $:5 ! ! ! !4 !@ !9 !. !b 8080a cpu 8228 system controller $: !)$: 8224 clock generator 5 5e $ $e 9 ) 5: % ;!< e h: := +;$ < !h$: > 9> 2:! 55 5!h e$ 2:! 9> 2:! 9> 9> > ; ' 1 * 00 + (% %' ( 3 00 + (' ' %(%% * 3 %(, %7 $:5 $: (( &# 00 )( !( '( )% ' %(%% * %( , %(, # $: $:5 (% '( (, $ 5 # $: (% '( (, $ i % ( $* /5 $ 1 ' % ( 6 # $:5 3( / (, 1 ( ('( , 00 + 3( ( i %% * ( % e $: ( (% %% & ( (' i %( , ( # + 3( ' (% ' ( % '( * ' ( * (% ( % '( # + 3( %% $: ( 00 )( !( '( )% ! ( & ,, ( , $: / 31 $: (% '( 3 /$ '6 3 , 1 %(, + % ( ( (( ' %% * ( % ('( , 00 + & % % / " 1 ' ( ' %%( , ; ' # 3 $: (% %% # + (% 3(( , / ' 1 ( * ( ! % $ '% * 00 + # (% / ' 1 ( * ( (% &(' & ' * * 5 ( % '( % 00 + % % (, (** ( % '( % , b % ( % '( % & ' % % '(*(' '( % 3( ( + k% & %' # 3 ( ( % (' ( "(%% table 7 % % (% * % 5 ( % '( %# ' %# ' % ( , 5 %% xr82c684 49 op-code (hex) mnemonic restart address (hex) b 0 !b ! 4 0 5b @ 5 9 0 b . 4 b 40 table 7. 8080a and 8085 cpu restart instructions used with vectored interrupts * # ' + ' ( % ' * * % 5 ( % '( %# ( 3( ,( " '( , (% ( % '( & ( , + , 3( ( / % %%1 * 3 %# , ' 3( ' / % %%1 '( " # (* ' /5b . 1 (% ! )% ( , $: '&' # (% ' ' % % 3( / @1 ' # + 3( . ( + , , ' 3( ' '( ( & % table 7 interfacing the 8080 cpu module to the xr82c684 quart for interrupt processing 00 + ' ' ' 80.0@ ( $ ! ( figure 11 % % ' ' ( ( *'( , 80.0@ 00 + * / " 1 ' ( ' %%( , please note that figure 11 only includes information pertaining to quart interrupt servicing. other circuitry (such as the 8224 clock generator, the address bus, etc.) have been omitted from the schematic. in this schematic, the quart interrupt service routine is located at 0020 16 in memory. additionally, the quart has been configured to operate in the i-mode. the function description of this circuit is presented below. 80.0@ 3( i % ( 00 + # & ,, ( , (% $: / 31 (% %(, (% ( ( '( (, $: ( * + ' 00 + % ' (% ' ( % '( # ( 3( %% '( 3 $: %(, * 00 )( !( '( )% ! ( (% ( # $: %(, * $: %(, * 00 ' ,(' / 31 $: $: %(, % 3 ( , ; ' # 3 $: $: ,(' / 31# * , 3( % ,(' / 31# & %% ( , * 5 5 ( % * :b@<@@ ! )% ** 4 (% /( ,1 * $: $: %(, % (% % ( % & ( (' i %( , ( (% ' ( % % (' ,# % %( %% $: %(, ' 5 ( % * 4 %% # # ( ( * (% (' 4 3( 3 * (% (' # !b ! ( % * 00 (' please note that, in this example, the value ?e7 16 ? is hard-wired into the input of u3. this value is the op-code for the ?rst 4? command. hence, once this data is gated into the cpu module, via the data bus, the cpu will load 0020 16 into its program counter and branch program control to that location. the interrupt service routine for the quart exists at this location in memory. xr82c684 4. $: $:5 ! ! ! !4 !@ !9 !. !b 8080a cpu 8228 bi-directional bus driver >'' sn74ls244 xr82c684 quart $: $: >'' 5 5 !$ !$ !$ !$4 !$@ !$9 !$. !$b ! ! ! !4 !@ !9 !. !b !)$: 4 @ 9 . figure 11. circuit schematic depicting approach to interface the xr82c684 quart to the 8080a cpu, for ?external? vectored interrupt processing (interrupt service routine resides at 0020 in memory) ( ' 00 + ' % 0 (** ( % '( %# ( ' % 0 (** ( ( ( (' % (% ' ' ( & ('( , ' # % ( figure 11 # & 3( ( , ' % * ' * 5 ( % '( % ( % * ! )** % % table 7 % ! )** % % & ( , $: '&' # & 3 ( %% '( ( i % ( % (' c.6.2.4 8085 microprocessor 009 + (% & $ (' ' %% # , ( (% ' 00 + * ' % 3 ( %(( * 00 009 ( ' ' ( ( , '6 2 * '( % * 0@ + ' (# ( , %6 ( i %# ( , 4 /( '1 ( i % ( ( %# ( , % * * ( ( (& 009 %( i( % % , ,(' ( ' )% %(, % ( # $# $e# 5# 5e # ( ( ((j ( ' # 009 ' ( % ( " %%-! )% ! !b '(*(' &# 3 0 (% * %% )% % ( % 3( 0 ( ! )% ; ' # b@<4b4 0 ( ' (% ( ( " %% ! % % xr82c684 4b figure 12 % % %' (' * 009 + 8 8 ! ! ! !4 !@ !9 !. !b ! ! ! !4 !@ !9 !. !b ! ! 4! @! 9! .! b! 0! 4 @ 9 . b 0 74ls373 4 @ 9 . b 0 4 @ 9 <5 + b9 .9 99 $: $: 8085 cpu 0 4 @ 9 $- ! e $ 5 $e 5e figure 12. a schematic of the 8085 cpu module xr82c684 40 8 8 + b9 .9 99 $: $: 8085 cpu $- ! e 5 <5 ! !b 0 9 %% ! ' @ 9 b 0 9 ! !b @ 74ls373 ! 0! 0 ! e xr82c684 5e g g;5g$ figure 13. schematic of the xr82c684 interface to the 8085 cpu module (memory mapped) figure 13 ( % % ' ( *'( , 80.0@ 009 + note that the xr82c684 quart, in this case, is memory mapped (e.g., the signals -memr and -memw of the cpu module are connected to the -rd and -wr pins of the quart). ; 3 # % ' c% % %( & ' ' 80.0@ (' + k% $- ,# %(, $ $e * + ' ' ! e ( % * # % '( & k% $: ( 3% ( & ( * (% *(, # '% (% % 3( %% ( " 3 *(, % 8085 cpu module interrupt structure 009 + % % !( ' /5" 1 > ' $ ' %%( , 009 % @ %6 ( i % ( % 99# .9# b9# $:# %6 ( i % ( + e (%'%%( , ( *'( , * ( % ('( , * ( (' % %' % # 3 & ' ' 3( %6 ( i % ( % * * %6 ( i % ( %f * % ( % % /!( ' $ 1 ' %%( , ( ( , ( i % % % /5" > ' $ 1 ' %%( , table 8 (%% % $ i % ( % ( ' ' (%('% * % xr82c684 4 input name trigger priority type acknowledge signal? address (hex) b9 + %(( 5, (,, !( ' : 4 .9 ;(, < ( % 4 !( ' : 4@ 99 ;(, < ( % @ !( ' : $: ;(, < ( % 9 5" > ' $: l /< 31 table 7 table 8. 8085 cpu maskable interrupt request inputs and their features direct interrupts 009 + ( % b9# .9# 99 /!( ' $ 1 i % ( % '(*(' &# (* & * % ( % %% # , ' * + (%# ' ( * ' ( % '( # (' & 3( & '( ( & '( '( & 3( ( 009 (' # ' % , ' '( % /!( '1 ( % ( ( (' 3( & % * /$ '6 3 , 1 ; ' # '' ( , table 8 # (* b9 ( 3 %% # /4 . 1 3 ( , ' * + # , ' 3 ' '( ( & % (% % %( ( % ' ' ( % (' ( ,( % '( ( & 009 + ** % ( ( ((j( # 3( ( % * %6 $ % (% ( (& (% * ' ( table 8 $ % % ( (& % & & / ( ,1 ( i % ' (' ( % / * i 1 (% ( , % (' & + # (% ( ((j( %' , ( % (' ( % i &# ( (% %%( 99 ( i % ' /( 1 ( % (' ( * (, ( (& b9 ( i % * # % % , ,( % (% ( (%- *( 3 table 8 % ( (' % 009 + 3( % / " 1 ' ( % ' % % ( " ' ( ' %%( , ( (' % * 00 + % section c.6.2.3 xr82c684 @ >'' ! !b ! !b $: .9 74ls373 <5 %% ! ' ( , < ,(' @ 9 0 8085 cpu xr82c684 b 9 $ 5 $e 5e $- ! e e ! ! figure 14. the xr82c684/8085 cpu interface for direct interrupt processing (interrupt service routine is located at 0034 in system memory) figure 14 figure 15 % 3 (** ' % ' % ( *' 80.0@ 009 + figure 14 % % %' (' 3 3( i % /!( '1 .9 $ 009 + $ (% '% # $ (' ( * % ,( 4@ . ( %&% & (% (% & %( ( *' ' (i # '% (% /$ '6 3 , 1 %(, ( *' xr82c684 @ 8085 cpu @ $: >'' $: sn74ls244 >'' 5 5 !$ !$ !$ !$4 !$@ !$9 !$. !$b ! ! ! !4 !@ !9 !. !b 4 9 . $: ! ! ! !4 !@ !9 !. !b !b ! ! 4! @! 9! .! b! 0! 4 @ 9 . b 0 74ls373 4 @ 9 . b <5 ! ! ! !4 !@ !9 !. xr82c684 figure 15. the xr82c684/8085 cpu interface for vectored interrupt processing (interrupt service routine is located at 0020 16 in system memory) figure 15 % % %' (' 3 3( i % /5" > ' 1 $ 009 + $ (% '% # $ (' ( * % ,( . ( %&% & c.6.2.5 68hc11 microcontroller *' % *( & * (' ' %# * % .0; (' ' % (% *( & * (' ' % ** % % * * 3( , (( %7 9 ( '( + + % 5+ -! xr82c684 @ + ) + + ! $ < ,(' 9. )& % ; % 6 + $- %'( '6 < ,(' -! $ +$ ( &% )% 5" %( %% %%-! $ 8$ 55 + 5 8< 58< ! !) + + 5 >; >< "! "! 0 = $ $ figure 16. block diagram of the mc68hc11 microcontroller figure 16 (% '6 (, * .0; .0; ' ' *(, ( /( , (1 ( /5" ( " )%1 $* (' (% ' *(, ( /( , (1 # ( .@= & % * %% %' (% ( $ please note that this does not mean that there is 64k bytes of memory, or other addressable portions within the device. .0; ' *(, * /( , (1 ( ' %% & ' % " * # (* % %( ( *' (% # % ( /5" ( " 1 .0; (% ' *(, ( 5" ( " & &( , ! !) ( >''# % ( , (' .0; ' %(%% * 9 (** ( * '( % 5' * % % ( * & (%'%% 3 port a + ' %(%% * 4 ( ( %# @ ( % ( ( '( ( (% (% % % ( &% * ( ( % ' % * + % '' * ( ( % % ( ' * '( %f * * ( % % ' * '( % port b + ) ' %(%% * 0 ( % $* .0; (% ( , ( %( , ' ( # (% * '( % % , % ; 3 # (* .0; (% ( , ( " ( " # (% 3( * '( % %% & * &- ( (' ( *'( , 0 9 port c + ' %(%% * 0 ( ( '( ( % e .0; (% ( , ( %( , ' ( # (% * '( % % xr82c684 @4 , % ( ( '( ; 3 # (* .0; (% ( , ( " ( " (% 3( * '( % ( " %%- % ! !b '(*(' &# ( , *( % * * & '&' # (% 3( * '( % 3 %% & + ) (% %% & * %%( , & (' % ( ' % ! ( , % ' * * & '&' # (% 3( * '( % ( ( '( % (% ' ( " ( % * %% ( b@<4b4 ' (' port d + ! ' %(%% * 0 ( ( '( ( % ; 3 # (% ' ' *(, % ' ( ( + ( $ *' +$# ( ('( % $ *' $ port e + 5 ' %(%% * ( @ 0 ( % ( , '6,( , ( (% ' ' *(, * '( % , % ( % ( % ' ( -! ' % ( % ( * ( *'( , 80.0@ (' * % ( % (%'%% 3 -irq (% (% /%6 1 ( i % ( $* (% ( (% %% ,# ,, / 31# .0; 3( ' , ' # 4 ( %&% & ' ( % (% % %( * ( % ( , ( ( % (' ( %( % (% '( ( & as/stra / %% 1 ' % ( " %%- % * + (% ( (% ,(' / (, 1 ( , *( % * * & '&' f ,(' / 31 ( , % ' * * & '&' $* .0; (% ( ( " ( " ( *' 9. & % * %% & %' # + % ) i( % % 3 ( figure 17. figure 17 % ( % % 3 80.0@ ' ' ' .0; * ( ( ( $* i %% ( # (% '( 3 $: ( 3( %% ,, 3# 3 (' 3( # ( # '% $ ( * + %% e (% '' % 3( ' ( " '( , (% ' ( % '( * ' ( * (% ( % '( # , ' 3( % (* '( # 4 ( %&% & % (% % %( ( % k% ( % (' ( %( % (% '( ( & 3( (%% ( '6 3 , %(, $ % # 3( c% ' %% % , ( % (' ( ' % (( '% % * k% ( i %# $: ( 3( , 3( * $ (' ( % ' %%( , ( % ( figure 17. , ,(' '( '( & i( , e# !# 55 %(, % * # * -e# 55# 5 ' '6 % ( figure 3. (% '( '( & % % ( ' ( figure 18. xr82c684 @@ 68hc11 xr82c684 74hc373 5 -e 0 9 e ! r$: $ @ ! !b @ 9 b ! !b %% ! ' 2 ! !) 9> $% ! figure 17. xr82c684/mc68hc11 microcontroller interfacing approach figure 18. glue logic circuitry required to interface the mc68hc11 c to the xr82c684 quart -e e 5 ' '6 ! 55 55 c.6.2.6 z-80 cpu ? 0 + ' ( *' ( , ( $ # (* ( + (% ( , ( $ % ; 3 # * %6 * / ' %% ' ( (&1# ( % %% '( 3( ? 0 + 3( % ( section c.6.2.1 c.6.3 z-mode interrupt servicing 3( ( , ( $ * 3( , 3 3 % * $ % % ( 6 / ? 1 ' % table 2 # ( ' *(, ( ? $ , # + ( *'( , ( , ( ? 3( * '( % * 3% ( , ( % ('( , $* i %% ( % ('( , * + # ( 3( %% $: ( ,# ,, / 31 ' + % ' ( i %# ( 3( (%% $= $ '6 3 , %(, '6 e + % % $= %(, ( (% ( * ( , (% ( i % (% % e % ' ( ' $= %(, # ( 3( # ( % % # ' ' % * * $ > ' ,(% % $> $> xr82c684 @9 ! )% + 3( (% /( ' 1 ( * ( f ( * 3( , 3 ( ,% % /( ' 1 ( * ( % ' * ( i % ,# 3 (' ( % % (' ( '( * $ (' ( * 3 %# , ' 3( ' '( * ( % (' ( ' ' (%(' * ? ( (% ( 3% % ( ((j ( i %% * % ( (' %# ( 3 % < % % % 3 % (' %f ' * % (' % ' *(, ( ? % ' ( ((j $ i % * ' * % (' % & ' '( , % (' % ( /(%& ' ( 1 % % ( figure 19. + $: $= $: $5$ $5 $= $: $5$ $5 $= $: $5$ $5 $= $: $5$ $5 $= > > ;$2;5 <e5 +$$h figure 19. a diagram of numerous quarts configured in an interrupt daisy chain (for z-mode operation) $ (( $: $= ( %# /? 1 % % % $5$ $5 ( %f 3 (' *( % * 3%7 iei - interrupt enable input (% '( (, ( (% & ( (* (% ' *(, ( ? $* (% ( (% ,(' / (, 1 %6 ( i %%# * (% # note: those interrupts which have been masked out by the imr are still disabled. however, if this input is at a logic ?low?, then all interrupts (whether masked or unmasked) are disabled. hence, iei can act to globally disable all quart interrupt requests. ieo - interrupt enable output (% '( (, (% & ( (* (% ' *(, ( ? (% (% &(' & ' ' $5$ ( * 3 ( (& (' (% ( (% / (, 1 (* * * 3( , ' (( % (' k% $5$ ( ( (% ,(' / (, 1 (' (% ' & i %( , ( % (' * + $* & * % ' (( % * % # $5 ( 3( ,(' / 31 note: once the ieo pin has toggled ?low?, and the cpu has acknowledged the interrupt request and has completed the interrupt service routine, the ieo pin will remain ?low? until the user invokes the ?reset ius? command (see table 2). therefore, if the quart is going to operate in the z-mode, the user must include the ?reset ius? command at the very end of the quart interrupt service routine. system level application of the iei and ieo pins figure 19 ('% % ( % * % ' ' ( /(%& ' ( 1 *% ( $ (% *(, # * % % (, % ( ( (& (% (% '% (% xr82c684 @. k% $5$ ( (% 3( >'' * # %6 ( i %%# * (% 3&% (' # ' c% (, * / (, % ( ( (&1 (' (% * 3 ( ( (& (% (% '% $5$ ( * (% 3 ( (& (' (% ' ' $5 * (, % ( (& e / (, % ( (&1 (' i %% ( # (% $5 3( ,, / 31 (% 3( ( # (% / 3 ( (&1 (' * (%%( , & ( i %% + (% / 3 ( (&1 3( ( ( * (%%( , ( % ( $5 ( * / (, % ( (&1 % ,, / (, 1 * ( ,# ' ,( # figure 19 # * (, (' (%# 3 (% ( ( (& (, % % 3 % ( ( (& '% (% /( i %1 ' ( (& ' (% & '( % * & * % * figure 20 % % (( , (, ('( , % i ' * % 3( '' ( , * 3( , $ i % * $: $= ! ! !b : > ( > ' $5$ $5 % $ figure 20. timing diagram illustrating the sequence of events occurring between the quart and the cpu during an interrupt request/acknowledge and servicing additional notes about z-mode operation ? ( (% % & ?( , + ( ' % ?( , ( ' % $ > ' ,(% # $ '6 3 , $= ( # $5$ ( # $5 * # figure 20 ' %( & ( ' % * % ?( , ( ' %# ( (( ( ( * % xr82c684 @b % ( ( # ? ( (% ' (* (% ( *' * 3( , ' %% % ? 0 (' ' %% $ 000 + 00. + 00. 090. + please note that it is possible to interface the 80x86 family of microprocessors to an i-mode quart, however, additional components and design complexity would be required in order to accomplish this ' (i - ' % ( *'( , ? % (' ' %% % (% % ( ( # ( * 3( , % '( % c.6.3.1 z-80 microprocessor ? 0 + ' %(%% * 0 ( ! )%# . ( %% )% % ' ( % ? 0 + (% & * "( ' %% 3 (' ' ' & ( *' ( ? $ (' (% (% '% ? 0 + ' ' *(, ( * (** /( %1 ? 0 (% % ( ( %% ' (' ( *' % * +- % ( % & ( '% (% %% % ( " figure 21 % % %' (' * ( * ? 0 + z80 cpu 4 @ 9 +;$ !@ !4 !9 !. > ! !b ! ! $: :$ ;< 5 $ ! e ) = e$ r) 55 ; 2:! 4 @ 9 . b 0 9 . b 0 . 9 @ 4 4 @ 9 . b 0 @ 4 40 4b 4. 49 4@ 44 4 4 4 @ 4 0 b figure 21 pin out of the z80 cpu device ? 0 + 3( % -e ( ( % 3 & $- ? 0 % i( % (( , ,(' ( ( *' ( ' & & ( (' % ( % ' # ? 0 + (' % ' 3( ' % %(, %7 5 & # 5e & e ( # $ $- + # $e $- + e ( $=- $: $ '6 3 , ( % 5' * % * '( % ' ( * !# e# $# 5 ( % figure 22 % % %' (' * ? 0 + # 3 (' % 3% 3 ' ' " ' ' % %(, % * % + ' ( % figure 22. schematic of z-80 cpu module 9 ! !b $: :$ e$ ) ;< ; ) = e ! 5 $ 55 $: $ $e 5 5e 2:! 9> +;$ '6 ( z-80 cpu interrupt servicing capability ? 0 + ' ( % 3 ( i % ( %7 :$ $: :$ (% /: %6 1 ( i % ( ( f $: (% /%6 1 ( i % ( ( %6 * ( *'( , # 3 & ' ' 3( $: ( ? 0 + ' ' *(, ( * (** ( %7 5" > ' !( ' /+ ( 1 > ' 5' * % ( % % $: ( * ? 0 + 3( (%'%% ( * 3( , % '( % xr82c684 @0 external vectored interrupt processing (interrupt mode 0) ? 0 + 3( ( (% ( (* /$ 1 ( % '( % " ' e $: ( (% %% & ( (' i %( , ( # + 3( ' (% ' ( % '( * ' ( * (% ( % '( # + 3( %% $: ,, / 31 $: (% '( 3 /$ '6 3 , 1 %(, + % ( ( (( ' %% * ( % ('( , e ? 0 + % ( $ # ( (% 3(( , / ' ( * ( 1 ! )%# * 3( , %% ( * $: $ (% '% * (% ( # (% / ' 1 ( * ( (% ' * * 5 ( % '( % ? 0 + % % (, (** ( % '( % 40; % ( % '( % & ' % % '(*(' '( % 3( ( + k% & %' # 3 ( $ % (' ( %( % table 9 % % (% * % 5 ( % '( %# ' % ' % ( , 5 %% % op-code (hex) mnemonic restart address (hex) b 0 0 !b ! 0 0 5b ; 5 0; 0 b 4; 4 40; 40 table 9. z-80 cpu restart instructions used with vectored interrupts (mode 0) * # ' + ' ( % ' * * % 5 ( % '( %# ( 3( ,( " '( , (% ( % '( & ( , + , 3( ( / % 1 %% * 3 %# , ' 3( ' / % %%1 '( " # (* ' 5b . (% ! )% ( , $: '&' # (% ' ' % % 3( ; ( % '( # + 3( . ( , ' , ' 3( ' '( ( & % table 9 % (% % %( * ( % ( , ( % (' ( ,( % (% '( ( & " * '( '( (j( , (% * * ( ' %%( ,# 3 ( ( *'( , # (% % ( section c.6.2.3 (% % '( (%'%% % ( *'( , 00 + (% "' % ' ' % 3( ? 0 + # ( (% ( , ( $ ? 0 (% ( , ( $ direct interrupt processing (interrupt mode 1) ? 0 + 3( ( (% ( (* /$ 1 ( % '( % " ' e $: ( (% %% & ( (' i %( , ( # + 3( ' (% ' ( % '( * 3 %# , ' 3( (' & 3( & '( ( & '( '( %(, * ? 0 + (' , ' 3( ' '( ( %&% & $ (% '% # , ' 3 ' 40 . ( & % (% % %( * ( % ( , ( ( % (' ( (% (' '( ( & ? 0 + % ( ( (' 3( & % * /$ '6 3 , 1 + c% ' %% % , $ (' ( # (( % '% % * ( i % % ( peripheral vectored interrupt processing (interrupt mode 2) ? 0 + 3( ( (% ( (* /$ 1 ( % '( % " ' (% ( / 1 (% & % * (* % 3(% % ' ' ( i % % * % ( % $: ( * ? 0 + (% ( 3% ( ( , (' ( (*& (% * ' ( ( # c% ( ( % ('( , e $: ( (% %% & ( (' i %( , ( # + 3( ' ( ' (% ' ( % '( ' (% ' ( % '( (% ' # + 3( %% $: %(, ( * ( (' ( % (' (% ,( ' ( ( , ( (' % ' $: % # ( 3( ' /( ' 1 ! )% (% ( ' 3( & + + 3( ' , ' '( * & ( ' please note that if the iei input to the quart (or zilog peripheral device) is ?low? then the quart (or zilog peripheral device) will be disabled from generating any interrupt requests to the cpu. " * (% ' (% % 3 ( figure 23 $ (% '% 80.0@ (% xr82c684 @ ' *(, ( ? (% ( *' ? 0 + e i( % ( % ('( ,# ( 3( %% (% $: (% '( 3( # ( # '% $: ( * + %% ' + % ' (% ' ( % '( # + 3( %% $: %(, (% 3( ( %% $= $ '6 3 , ( % * %% $= %(, (% ( * & " '&' 3( /$=1 /$ '6 3 , 1 '&' # ( % % $= %(, # 3( ' ' % * * $ > ' ,(% % $> $> ! )% (% 3( & + # , ' 3( ' ( ( % (' ( $ '% * ? 0 + # (% '( (% . ( %% 3 (' (% ( * * 3( , most significant byte least significant byte bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 % * $ ,(% 3( ( + b % (, (*(' )(% 3( ( $ > ' ,(% % * table 10. the relationship between the contents of the interrupt vector registers (of the quart) and the location of the interrupt service routine (z-80 cpu) note: the lsb of the ivr is always set to ?0? once read by the cpu. interrupt service routines must begin at even addresses. (( &# % % 3 * ' % -% % ( $ ,(% * + # ( , ( 3 ( (& ( %% ! ' ( '( & 9 4 @ ! !b ! !b g $: $: e ! 5 $ e ! 5e $= z80 cpu xr82c684 5 $: $5$ $5 * >'' (, ( (& ( figure 23. schematic of an approach to interface the quart to the z-80 cpu (for z-mode operation) xr82c684 9 c.6.3.2 8086 microprocessor 00. (' ' %% (% . ( (' ' %% *' & $ ( figure 24 % % ( (, * (% $ please note that in this figure, pins 24 - 31 have some additional labels, located off to the right of the package. these additional labels will be explained later in this text. $ 3 , , % 6 ( ' * (% $ 3 & ( "( , * '( % * & * % ( % (% (' ' %(%% * . ( ! )% ( %% )% ! )% (% ( " 3( 3 . %% )(% 9 * ! !9 %% )(% . ( " 3( %% (% 4 . * .-4# b-@# 0-9 -. * % ( % %% ( % ( , *( % * * & '&' ; 3 # ( , % ' * * & '&' # % ( % 6 ( * '( % ,# ! !9 ' % ! !9# .-4 -. ' % 4 . % ' , * ( " ( % (% ' & :- 8 ( ( e (% ( (% (, # /( 1 (% % ' ( % @ , 4 6 ' *( (( % % 3 :- 8 l ' ( table 11 e 00. + % ( (% # ( % % ' % & %(( * 009 +# i( % & %% ' ' '6 , * + figure 24. pin out of the 8086 microprocessor device 2:! !@ !4 ! ! ! ! !0 !b !. !9 !@ !4 ! ! ! :$ $: <= 2:! 55 5!h 5 <= - 2 - 2 ! :-8 );5-b -. 0-9 b-@ .-4 !9 > 8086 cpu 9 . b 0 . 9 @ 4 4 @ 9 . b 0 @ 4 40 4b 4. 49 4@ 44 4 4 4 @ 4 0 b $: <5 !5: !- -$ e ; :- 8 (% 3# 00. + (% ( , ( /"1 (% (% ( * ' " ('( % ( 3 (' 00.+ i( % % * 00b (' ' %% :!+ $ (% # % '( % ' 000 (% i( , & $- ' % %(, % 00. + ' ( % 3 ( i % ( %7 $: :$ :$ (% '( (, / %6 1 ( i % ( f $: (% /%6 1 ( i % ( $* 00. + (% ( , ( /( 1 # $: $ '6 3 , ( (% ( +( @ % figure 20 ; 3 # (* 00. + (% ( , ( /"1 # $: %(, % ( * # # ( % ( 000 % ' table 12 % % ' %% %% 000 '( % % # # /"1 %% %(, % pin number mn/-mx = 1 (min mode) mn/-mx = 0 (max mode) @ ; '6 3 , $: $- + $ e ( $- + $e ; : '' %% ! & ! e ( & e +%%( : table 12. 8086 processor state/8288 bus controller active output as a function of -so, -s1 and -s2 figure 25 figure 26 % 00. + # 3 ( , ( /( 1 /"1 %# % '( & xr82c684 9 ! !b !0 !9 $: $: <5 ;'' ! ! figure 25. schematic of the 8086 cpu mode (min mode) xr82c684 9 :- 8 <= !5: !- <5 $: ! e $ $e 8288 bus controller 74ls373 74ls373 5 5e $ $e ! !b !0 !9 $: <= ! !b !0 !9 b 0 9 ! ! 8086 cpu figure 26. schematic of the 8086 cpu mode (max mode) 8086 c interrupt processing $* ( ' i( % ( % (' * + # ( 3( %% + k% $: ( & ,, ( , ( (, ' + % ' (% ' ( % '( # ( 3( %% $: ( (* ( , ( /( 1 % # # ( % /1 % $ ( '% # $= ( * ( 3( %% ' (% %# ( ( , ( (% " ' ' /( ' 1 & ! !b * % 00. + 3( (% ( & (% & @ ( ( '( * ( % (' ( ( & ( ' (% /( ' 1 (% 0 (% 3( # 00. + ' '' 9. (** ( ' % 99 (( &# %( ' ' ' (% ( ( & /@1# % (% " ' % *( % = & * & * $ (' ( %-a figure 27 % % %' (' * 80.0@ ( *'( , /( 1 00. + (' please note that the quart has been configured to operate in the z-mode. therefore, the user must account for the iei input to the quart device. xr82c684 94 figure 27. schematic of the xr82c684 quart device interfacing to a ?min? mode 8086 cpu device ! e ! !b !0 !9 $: <5 ; $: ! !b 9 b %% ! ' $: $= @ $5$ ;(, + ( (& ! (' xr82c684 ! ! d. timing control block (( , ) '6 3% % % '(*& ( % -% 3(% % %( ' ( 3( ( ' ' (( , ) '6 ' %(%% * * 3( , %7 %'( ( '( )( 2 % . ( -( % 0 5" $ +( % ' '6 %( % ' ( %# ( ' & '6 ' ,(% % 47 8% ) '% * ' "(& * k% (( , ) '6# '6 (, # * (% '6 % (( ( 3 %# % % ( figure 28 figure 28a xr82c684 9@ figure 28. block diagram of the portion of the quart timing control block which services channels a and b + % ,(% % # < - ( d 47 8 " 47 8 " 47 8 ") 47 8 ") $+. 8) $+9 8) $+@ 8 $+4 8 $+ g58 !(( & . 8 8) p@ .q )( 2 pbq %'( ( '( 8-<= 8 !(( & . xr82c684 99 figure 28a. block diagram of the portion of the quart timing control block which services channels c and d + % ,(% % # < - ( d 47 8 " 47 8 " 47 8 "! 47 8 "! $+@ 8! $+4 8! $+ 8 $+ 8 $+ g58 !(( & . 8 8! p@ .q )( 2 pbq %'( ( '( 8-<= 8 !(( & . figure 28 % % (, * ( * (( , ) '6 3 (' % (' % % ) e %# figure 28a % % (, * ( * (( , ) '6 3 (' % (' % % ! please note that each ?half? of the timing control block consists of a 16-bit counter/timer, a baud rate generator, a set of four external clock inputs and four 32:1 mux?s. each ?half? of the timing control block shares the output of the oscillator circuit. 5' * (( , ) '6 (% (%'%% 37 d.1 oscillator circuit: ' &% %'( (% &(' & ' ' " & ' %% 8-<= 8 ( % %'( ( '( 3( ( ' ( * '( % % * % ' &% %'( # ** % % ( , %'( ( , %(, # * % & * )( 2 %# -( % ' &% < %(, * i '& * 3 ;j 0 ;j (% i( * ( * ; 3 # ' &% < %(, * i '& * 4.0.@ ;j (% i( * , ( * % ( %# % ( table 15 # & )( 2 % (( &# * i '& * b4b ;j (% i( * , ( * % ( %# % ( table 15 # & )( 2 % figure 29 % % 3 ' %' ('% * 8< %'( '( '( & * ' &% % 3( * i '( % * 4.0.@ b4b ;j xr82c684 9. figure 29. recommended schematics for the xtal oscillator circuitry xr82c684 8 8 b4b;j + % &% 7 9 n & s 9 7 9 n & s 9 xr82c684 8 8 4.0.@;j + % &% 7 n & s 9 7 n & s 9 7 7 note: the user also has an option to drive the oscillator circuit with a ttl input signal, in lieu of using a crystal oscillator. if this approach is used, the ttl must be driven into the x1/clk pin, and the x2 pin must be left floating. $* % %( % % % * %( , ' &% %'( # figure 30 % % ' ' %% & '( '( & '' (% (% c '( 8 8 xr82c684 h 74hc14 8 ( % * % 4.0@;j figure 30. a recommended schematic to drive multiple quarts from the same crystal oscillator note: the user is urged not to use the 74ls14 schmitt trigger inverter in lieu of the 74hc14 device. the input of the 74ls14 tends to load down the oscillating signal from the quart, to the point that the schmitt trigger inverter can no longer change state or respond to the oscillator signal. xr82c684 9b d.2 bit rate generator 5' * 3 )2% )( 2 % '' % (( , * %'( ( '( , ' '6 %(, * 44 ' & % ' ('( ( % ,( , * 9 % 4@ 6 % please note that the brgs will only generate these standard bit rates if the oscillator circuit is running at 3.6864 mhz (for the bit rates presented in table 15) or running at 7.3728 mhz (for the bit rates presented in table 15a). the actual clock frequencies output from the brgs are at 16 times these rates. % ' % ' * 3 (** % % * ( %# , * )2 (% % '( (% & % ( , ' ( , pbq pbq (%( , * % % % * )( %# * )2# (% % ( (%'%%( * '6 ' ,(% % % ( section d.5 '6 (, * )2 '( '( & * ( % )# * ( % ! % ( figure 31 figure 31 # % '( & %'( ( '( 8-<= 8 )( 2 % ) pbq )p47q 47 8 8) )pb7@q 47 8 8) pb7@q 47 8 8 p47q 47 8 8 figure 31. block diagram of the bit rate generator portion of the timing control block, for channels a and b xr82c684 90 %'( ( '( 8-<= 8 )( 2 % ! pbq !p47q 47 8 8! !pb7@q 47 8 8! pb7@q 47 8 8 p47q 47 8 8 figure 31a. block diagram of the bit rate generator portion of the timing control block, for channels c and d d.3 counter/timers (( , ) '6 % ' ( % 3 . ( -( % -d -d 5' - (% , . ( 3 ' 3 (' ' % * % (( , % ' % % (% ( figure 32 figure 32a % % '6 (, * '( '( & % ( , -d -d# % '( & % '( * % (( , % ' % * -( % d d ' & 3 (( , ( p.7@q p.7@q# % '( & please see 4 and 4 for the relationship between the counter/timer mode, the timing source and acr[6:4] for counter/timers #1 and #2, respectively. - # * -%# (% ( '6 ' ,(% % * % % , ( , * * %( % ' ( % please note that the quarts, packaged in the 44 pin plcc have limited options in regards to timing source, as depicted in table 13 and table 13a. xr82c684 9 - ( d + % ,(% % # < $+ !(( & . 8 8) p@ .q -gg!h +4 47 8% !(( & . %'( ( '( figure 32. a block diagram of the circuitry associated with counter/timer #1 - ( d + % ,(% % # < $+ !(( & . 8 8! p@ .q -gg!h + 47 8% !(( & . %'( ( '( figure 32a. a block diagram of the circuitry associated with counter/timer #2 xr82c684 . bit 6 bit 5 bit 4 c/t mode timing source 5" $ $+ 8 8 '6 * %( 8) 8 '6 * ) %( 8-<= $ !(( & . ( 5" $ $+ ( 5" $ $+# !(( & . ( 8-<= $ ( 8-<= $ !(( & . note: the ?shaded? options are only available in the 68 pin plcc. table 13. acr1[6:4] bit field definition - c/t#1 bit 6 bit 5 bit 4 c/t mode timing source 5" $ $+ 8 8 '6 * %( 8! 8 '6 * ! %( 8-<= $ !(( & . ( 5" $ $+ ( 5" $ $+# !(( & . ( 8-<= $ ( 8-<= $ !(( & . note: the ?shaded? options are only available in the 68 pin plcc. table 13a. acr2[6:4] bit field definition - c/t#2 " ( sections d.3.1 d.3.2 , (' & * % -( - ; 3 # (% " ( % -( d d i & e ( # (%( '( % 3( 3 3 -% d.3.1 timer mode: please note that of the two c/t modes, the timer mode is the only mode which is relevant to the function of bit rate selection. however, for completeness, the counter mode is also discussed below. $ ( # - '% % , (( , % %i 3 3 % ( (% 3(' ( ' '6 ( % * ' % * -( ,(% %# < - ' % % , ( , ( ' .8 ' '6 * & ( ( & )2 %i 3 # (,( ( , * -d (% + ( # +4 e %# %i 3 # (,( ( , * -d (% + ( # + $* - (% , ( ( # * i '& * % ( , - %i 3 ' " %% % * 3%7 - i '& l frequency of selected timing source tp ctur qt 0 + p ctlr q 3 7 p q l ' % * ,(% ( '( * p<q l ' % * < ,(% ( '( * ( ' - (% % .8 ' '6 %(, & '( '( &# % ( , ( (% -. * i '& * - %(, * # ( # ( * - ' " %% % * 3%7 frequency of selected timing source 4 t p ctur qt 0 + p ctlr q ' % * < ,(% % & ' , & ( # 3( & ,( 6 ** ' " * '&' * %i 3 - ,( % ( %( , % ( -< ' ( * %% (,, / :51 ' table 1 - % ' ( % & % % i / :51 ' '% % - ( ' (( , '&' ,( 3 (( , '&' %( , ' % % ( < :5 5!h %% (# ( $ % ,(% % $p4q $p4q# (% % ' ' '&' * %i 3 (% 3% % * - % ( (' ( , # (* ' (( (% , , ( ( ( %6 ,(% % $ $ $p4q - $p4q ' ' & (%%( , ( %% (,, /+ :51 ' table 1 $ $5 # 3 # ' % ' & % - xr82c684 . d.3.2 counter mode $ # - ' % 3 * % % 3 ( ( -<# ,( ( , ' ( * / :51 ' :5-5!h %% ( $p4q $p4q (% % ' ( , ' * . - 3( ' ( ' % . * 3 3( " ' ( , . ( ( (% % & + ( /+ :51 ' $* + ( +4 (% , * -d# 3( ( (, ( ( ' (% ' # 3 (' ( , % 3 $ % (, % $p4q (% ' 3 - (% % ( /+ :5 1 ' / :51 ' 3 ( ' (% ( , % % ' 3( % ( -< + & ' , ' % * < & ( 3 ' 6 % ** ' & * % % i :5 ' $* 3 % , ( % % % % * " '&' d.4 external inputs ( .0 ( +< '6, & 3% * % * $ + ( % $+4 $+. $+ $+@ % % ( ' " ( % (( , ) '6 % (( , % ' % * %( % ' ( % * * ' % % ( % ( ( @@ ( +< please note that the user can specify whether a clock signal, applied to one of these external inputs, is a 1x or a 16x clock signal; via the clock select registers (see below). for a more detailed discussion on the input port pins and their function, please see section e. d.5 clock select registers, csra, csrb, csrc, and csrd $ figure 32 figure 32a # ' ( * '6 ' ,(% % 47 8k% '6 ' ,(% % % % ' % ' 3 (' ' '6 %(, % 3( ( %( % ' ( % * ' % % 3 % % ' 44 (** % ( % * )2# -( # % " ( % (( , % ' * %( % ' ( % table 14, table 15 table 15a % ( % ( 3 ' % * % ' '6 % ' (( , %( % ' ( % bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ' ( '6 ' %( '6 ' table 15 table 15a table 15 table 15a table 14. bit format of the clock select registers, csra and csrb xr82c684 . field bit rate pb7@q pbq l pbq l pbq l pbq l p47q 8l 8l 8l 8l 9 b9 b9 9 4@9 4@9 4@9 4@9 9 9 4 4. 4 4. . @@= . @@= 00= 00= 9 9b.= 9b.= @ 9= @ 9= @0 @0 @0 @0 b 0 0 b . . . . 40@= = = 40@= ( ( ( ( 5" .8 5" .8 5" .8 5" .8 5" 8 5" 8 5" 8 5" 8 note: the ?shaded? options are only available in the 68 pin plcc table 15. bit rate selection via the clock select registers, csr[3:0] and csr[7:4] for oscillator frequency of 3.6864 mhz field bit rate pb7@q pbq l pbq l pbq l pbq l p47q 8l 8l 8l 8l 9 9 . . . . @ 4 4 @ . b . b 00= 00= @ 9b.= @ 9b.= 9= @ 9= @0 4@= @0 4@= . . . . @@= 4. 4. @@= = = = = b.0= 40@= 40@= b.0= ( ( ( ( 5" .8 5" .8 5" .8 5" .8 5" 8 5" 8 5" 8 5" 8 note: the ?shaded? options are only available in the 68 pin plcc table 15a bit rate selection via the clock select registers, csr[3:0] and csr[7:4] for oscillator frequency of 7.3728 mhz xr82c684 .4 + % table 15 table 15a ' % * % % '(*& * 3( , %7 pbq pbq % %(, (*(' ( ) * "( ( & ,(% % 8 5" ( pbq pbq ) * "( ( & ,(% # ' %( & , & 3 (( , """"""" """"""" # ( % ' # % '( & : 7 %**(" % ( & " %%( " l k ' x - the select extend bit 5' %( ' ( # 3( ( % " ( ' % ' & 3 (( , ( ' k% ,(% , (% ( * ( ' * ( table 2 table 16 % (j % % ' %# ( ** ' 5" (% register contents resulting action ,(% # 0 " )2 ' 5" )( 8 l ,(% # " )2 ' 5" )( 8 l ,(% )# ) " )2 ' 5" )( 8 l ,(% )# ) ) " )2 ' 5" )( 8 l table 16. command register controls over the extend bit note: if the user programs either nibble of the clock select register (csrn[7:4] or csrn[3:0]) with values ranging from 0 16 to c 16 , then the user is using the brg as a source for timing. how- ever, these standard bit rates (presented in table 15) apply only if the x1/clk pin is driven with a 3.6864 mhz signal. if a signal with a different frequency (fo) is applied to the x1/clk pin, then the quart channel is running at the following baud rate: actual baud rate = p table 9 baud rate value qt fo 4.0.@ mhz ( * (% 3 ;j b4b0 ;j (( &# % ( '% * % %# ' * i '& * ' '6 %(, 3( . ( % % % <(6 3(% # ( %# * )2% % % ( table 15a & & (* 8-<= ( (% ( 3( b4b0;j %(, $* %(, 3( (** * i '& * (% ( 8-<= ( # ' (% ( , * 3( , actual baud rate = p table 9 a baud rate value qt fo b4b0 mhz ( * (% 3 ;j b4b0 ;j ( &# % ( %# , & )2%# % ( table 15 table 15a # & & (* (% ( , ( /!( ' &% % '61 % table 2 $* (% ( , ( /!(( &% % '61 # 3( * * % ( table 15 table 15a 1x vs 16x clock signals % /8 '61 /.8 '61 ( , (% " * # ( (% ( (%'%% ( ( , %(, (*(' ' /.8 ' '61 % % ' ( % ( & *' * . e % /8 ' '61 & % % %(, % ' ( ( (% ( % ' ' & ' ' , '' '& 3 ( % ' ( ( % * .8 ' '6 ( ( * 8 ' '6 * 3( , , % 3( ' (*& % % ' ( ( * ' % (% ' '6 & ' (( , % ' * (( , ) '6 $* (% ' ( (% '( (% ' (( , * % ( %( # %( (% % ' '6 & (% 3 ' (( , % ' ; ' # (% , ' '6 * i '& * ' ( (% "' & % % * %( (% (% ' ' (%(' * %& ' % % ( ' ('( , ' ( %( , ' ( %( "' & % # %**('( (** ' % ( * i '( % * 3 ' '6 % ' % ' ' ( %( ' ' ( ( % ( ' (( , ' %%# % % ( * 3( , (%'%%( % 3 % ( %(%%( %&% % (' ( figure 33 (% %&% ' %(%% * %( 8# ' ' ( 8 xr82c684 .@ %( 8 ' ( 8 8 '6 8 '6 figure 33. example of a serial data transmission system < % * %% ' ( (% ' '6 & % ' (% % (, & *% * %( # ' ( (% & % ( , % ( ' ( ( figure 34 % % % % * (% figure 34. receiver (1x) sampling, if the rx clock is slightly faster than the tx clock figure 34 % 3% % ( % ( 3 ' ( k% % ( , ( ' % ( ( (% ' ,( , $ (% '% # ' ( (% % ( , ' % ( (# ( ( ( ( ( # 3( ' %'' %%( ( (% (% 6 3 % ' ( (* $* (% ' '( * ' ( (*# 3( & % ( %(%%( ' ( * (% % ( # % (' 3 ( figure 35 xr82c684 .9 actual data received data figure 35. illustration of an error due to receiver drift 01 01 01 00 1 0 1 0 10 1 0 1 figure 35 % 3% ' ( % ( , (, ( % ( , * 3( ( $ (% ( %( , # ( (% *(, # ' ( % $ % ' ( (* ' % (% ' ' ( (% % 3 %( ' '6 $ , ( # * (% / ' ' 1 %&% (% * '( * (( , (** ' % 3 8 8 ' ' '6 %(, % ; 3 # ( ' ' * ' ( ! (* ( ((j )5 ( , % ( %(%%( # & % ( 6 ' # & ' ( % ( , * ( e (% * (% & # ' ( # '( * (# 3( ,( % ( , (% ( & % ( , *' &(' &# * % % & %# (% % *' (% . 80.0@ (' % '' % .8 ' ( % ( , * ( * # ( % (' %# 3 ' ( '% '' ' * (# ( ' ( 3( ,( % ( , (% ( & *' * . ; 3 # * b .8 ' '6 ( % % % # ' ( 3( %% (% ( 3( ( ( ( ( * ( ( # 3( ' % % ( , * ( * % % i (% ( # , * ' ' # ' ( 3( % % ( % 8 3&# ' ' ( % ' # 3 ( ( % ( ( * (# ' ( 3( # * ( # ,( % ( , % ( ( ( ( % figure 36 * ' ( % ' ( + (# ( 3( 3( '' ' * ( ' ( % ' # (% % ( , ' (% xr82c684 .. b .8 ' '6 ( % % % ( ( * )( )( + ( figure 36. the typical sampling pattern of each receiver within the xr82c684 device % ( , ' (i ((, % & * % ( ( % & ( , c% ' ( % ( , ( # ( ( * ( ( %# ' ' ' ' %(% (% ' (% %'' %%* * 3 % %7 $ ** % ( (' ' '( ' ( % ( , ( $ ((% ' ( (* 3 % ( , ( c% % &(' & % (% 0 ( ' ' n (& + (% * # (* % % '% ' ( * . f '( * (# ' ( 3( ,( % ( , . " . l 94#. ;j ; 3 # ' ' ( % % b 94. 6;j ' '6 % # ( 3( 6 (% '( % ( ( * ( (% ( # 94. 6;j ' '6 %(, (% (( & . , % ' '6 . ;j * ( ( , (% * ' ' 80.0@ (' % ,( % % ( ' " ( ' '6 %(, % ( 8 .8 ' '6 %(, e % (% ,( ' (' % ( 8 .8 ' '6 %(, '6 ' ,(% %# % (% (% 3&% % .8 ' '6# ( ((, ** '% * ' ( (* % (% * (% % 8 ' '6 * % * # %% ( ' ( , % ( % (% %& ' % 3( ' ( 8 ' '6 d.6 application examples using the timing control block $ ' (*& % * %% % 3( ( (( , ) '6# " % ( ' example a: using the brg % % 3(% % ' ( %( * 9 6 % ( % % * 3( ,7 % 4.0.@ ;j ' &% %'( ' %% 8-<= 8 ( %f (( , 4.0.@ ;j < %(, ( 8-<= ( 3( 8 ( * ( , e ( . ,(% (% % 3( % %( )2 ' 5" ( 8 l 4 e ( 0 . ,(% (% % 3( % ' ( )2 ' 5" ( 8 l @ e ( """"""" (% % % '% /)( 1 d table 15 * (% % xr82c684 .b e %**(" % ( & " %%( # " % / k ' 1 * ( & " %%( 9 e ( 00 . (% % % % ' ( %( ( * 9 6 % table 14 table 15 example b: programming the bit rate via the counter/timer % % 3(% % %( ' ( .9 6 % ( ) please note that this particular bit rate is not offered by the brg. in this case the user can do the following. ! ( @ ;j < %(, ( 8-<= ( # 3 ( 8 ( (% * * ( , e ( . . < (% % % % % ( - d , ( , %i 3 * * i '& l @ ;j-pq l ;j 4 e ( p.7@q (% 3( % -d ( ( # % ' (( , % ' * - 8-<= ( @ e ( !! . ) (% 3( % '(*& (( , % ' * ' ( %( * ) 3( ( * -d please note that when the quart is programmed in this configuration, the c/t output represents a 16x over sample of the transmitted and received data. therefore, the chip circuitry will divide the 1 mhz square wave by 16, just like for clock signals originating from the brg. thus: bit rate = 1 mhz/16 = 62.5 kbps. example c: using the external input ports % # ( (( ( , ) .9 6 % % 5" )# -% 3 % %( ' ( % ( % % * * % % % ( 5" )# , 3( * 3( ,7 e ( """""" + + *(, ( ,(% (% % 3% ;j %i 3 * -d +4 note: x = don?t care %**(" % ( & " %%( 5" & ' ' +4 ( $+4 $+@ ( % & &( , ;j %i 3 ( % 3 ( ( % 4 e ( . (% % 3( % '(*& (( , % ' * %( ' ( * 3( ( * ( ( % $+4 $+@# % '( & (( &# (% % 3 3 % % ( %(, 8 %(, % ; ' # (% ((%( & . * (% %(, * # ( * (% % please note that if the user were to apply this example, he/she would be responsible for ensuring that the incoming serial data stream is synchronous with the 1 mhz (1x) clock signal; in order to minimize bit errors. xr82c684 .0 d.7 explanation of clock timing signals % * (% % '( (% " ( ! % '(*('( (( , ) '6 % $ %# (% % c ' % % ' * ' %( ' *%( & % % % 80.0@ ! % % * 3( , % '(*('( %# ( / 5<5$< ;5$$1 limits symbol parameter min. typ. max. units <= 8-<= 5" ;(, < 3 ( % *<= 8-<= &% 5" i '& 4.0.@ b4b0 ;j -( 5" '6 ;(, < 3 ( $+ $ % * -( 5" '6 i '& $+ $ b4b0 ;j 8 8 8 5" ;(, < 3 ( ( $+# $+4# $+@ $+9 % *8 8 8 5" i '& ( $+# $+4# $+@# $+9 *8 .8 .8 . ;j *8 8 8 ;j figure 37. clock timing : 3 * " ( * ' * % %7 tclk - x1/clk (external) high or low time &% & (' ,(' , ' * (% '( '( & * # ( ( ((% <= *<= ( % (' 3( * '( & (% c% ' % 3 (( * ( %(, ( , 8-<= ( % %( (, 3 % % fclk - x1/clk crystal high or low time (% % '(*( % , * * i '( % (%%( 8-<= ( # ( ( ' &% %'( ( < ( %(, * # % ' & & 3 b4b0 ;j (% ( tctc - counter/timer external clock high or low time - ip2/ip10 input (% ' % 3 (( * ( %(, # ( , ( $+ $+ ( %# * % & -( %# ' %( (, 3 % % please note that this limit has no relationship with the parameter trtx, which is another spec associated with the ip2 input. fctc - counter/timer external clock frequency - ip2/ip10 input (% ' % (( * ( * i '& ( , ( $+ $+ ( %# * % & -( % % ' %(' & % % %(, 3( * i '& b4b0 ;j ' ( $+ $+ ( %# %( & & -( % trtx - rxc and txc (external) high or low time - via ip3 - ip6, and ip11 - ip14 (% % ' ' % 3 (( * ( %(, # ( , ( 2 + % $ +( %# $+ $+9 $+ $+@# * % % %( ' ( '6 % ' # ' %( (, 3 % frtx - rxc and txc (external) frequency - via ip3 - ip6, and ip11 - ip14 (% % ' ' % ((% 8 .8 " %(, % % ' '6 %( % ' ( % $* % 3(% % % 8 ' '6# -% ' & & %(, 3( * i '( % ;j (% ( 3( % % ( ( * % % 5" $* % 3(% % % .8 ' '6# -% ' & & %(, 3( * i '( % . ;j ( ' (% %(, (% .8 %(, # (% 3( % ( ( * % xr82c684 . $ % &# (( , '6 ,( % % ( (& , ( & & % %( % (( , ) '6 ,( % % '' %% * 3( , % ' %7 44 (** % ( % ( )2 3 -( %# 3 (' ' ' *(, , ( % 3 (' ( * )2% $ % (( , ) '6 ( % $ + ( % 3 (' 3% % * " ' '6 %(, % , '% ( e. input port $ + ' %(%% * . ( ( % $+ $+9 $ + ' % % , % ( ' , % % * % ( % * % '( * '( % ' % * ( % (% ' ' & + & ( , $+ ,(% * ,(' % % * $+ $+b ( ( % $+ ,(% * ,(' % % * $+0 $+9 ( ( % (, ( %(, $+ ( % % ( ,(' /1 ( $+p q ( %(( # 3( ( $+ ,(% * $ + ( % $+ $+b (( &# (, ( %(, $+ ( % % ( ,(' /1 ( $+p 0q ( %(( # 3( ( $+ ,(% * $ + ( % $+0 $+9 e.1 alternate functions for the input port table 17 %' ( % % % * ( ( %# %' % ' '6 ( % * 3 ' %(, % ( ' % ( * % & % 3 , * '( * $+ ,(% % 3( % 3 ,(' % ( # , %% * (% , * '( input port alternate function(s) approach to program alternate functions $+ 7 ( * note: this input is active low, for the cts func- tion. $+ ' , * '( % ( & % ( , p@q l ( (%'%%( (% * '( # % % section d.3. $+ )7 ( * ) : 7 (% ( (% '( < 3 * * ' ( $+ ' , * '( % ) ( & % ( , )p@q l ( (%'%%( (% * '( # % % section d.3. $+ g 587 -( d 5" '6 $ $+ ' , * '( % " ' '6 ( * -( d & % ( , p.7@q l p# # q ( (%'%%( ( ** ' * (% '( % % section d.2 $+4 8 g 587 5" '6 ( * %( $+4 ' , * '( % " ' '6 ( * %( * & % ( , p47q l p# # # q ( % .8 '6# p47q l p# # # q ( % 8 '6 $+@ 8 g 587 5" '6 ( * ' ( $+@ ' , * '( % " ' '6 ( * ' ( * & % ( , pb7@q l p# # # q ( % .8 '6# pb7@q l p# # # q ( % 8 '6 $+9 8) g 587 5" '6 ( * %( ) $+9 ' , * '( % " ' '6 ( * %( * ) & % ( , )p47q l p# # # q ( % .8 '6# )p47q l p# # # q ( % 8 '6 $+. 8) g 587 5" '6 ( * ' ( ) $+. ' , * '( % " ' '6 ( * ' ( * ) & % ( , )pb7@q l p# # # q ( % .8 '6# )pb7@q l p# # # q ( % 8 '6 $+b : :- xr82c684 b input port approach to program alternate functions alternate function(s) $+0 7 ( * note: this input is active low for the cts func- tion. $+0 ' , * '( % ( & % ( , p@q l ( (%'%%( (% * '( # % % section g.3 $+ !7 ( * ! : 7 (% ( (% '( < 3 * * ' ( $+ ' , * '( % ! ( & % ( , !p@q l ( (%'%%( (% * '( # % % section g.3 $+ g 587 -( d 5" '6 $ $+ ' , * '( % " ' '6 ( * -( d & % ( , p.7@q l p# # q ( (%'%%( ( ** ' * (% '( % % section d.2 $+ 8 g 587 5" '6 ( * %( $+ ' , * '( % " ' '6 ( * %( * & % ( , p47q l p# # # q ( % .8 '6# p47q l p# # # q ( % 8 '6 $+ 8 g 587 5" '6 ( * ' ( $+ ' , * '( % " ' '6 ( * ' ( * ) & % ( , )pb7@q l p# # # q ( % .8 '6# )pb7@q l p# # # q ( % 8 '6 $+4 8! g 587 5" '6 ( * %( ! $+4 ' , * '( % " ' '6 ( * %( * ! & % ( , !p47q l p# # # q ( % .8 '6# !p47q l p# # # q ( % 8 '6 $+@ 8! g 587 5" '6 ( * ' ( ! $+@ ' , * '( % " ' '6 ( * ' ( * ! & % ( , !pb7@q l p# # # q ( % .8 '6# !pb7@q l p# # # q ( % 8 '6 $+9 : :- note: ?shaded? input port pin and alternate functions are only available in the 68 pin plcc package. table 17. listing of alternate function for the input port e.2 input port configuration registers (ipcr1 and ipcr2) , * % ' % ( * ( ( % $+ , $+4 $+0 , $+ % ( % % & 40@ 6;j * )2 @ 6 % " . (, 3 3 (, %(( % ( %( , % 3 ' '6 ( % "( & 9% 3( , ' % ( , ( ( ( ( ' , ,(% $+ $+ 3( % # , ( & % & ' , * % % % % 9% ( * * ' * $+% * 3% %% (% ( ( * $+ $+pb7@q $+pb7@q ' 3 ,(% (% & + & ' , * % ' % , , ( ( /$ + , * 1 ( bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ! $+4 ! $+ ! $+ ! $+ $+4 $+ $+ $+ l: lh % l: lh % l: lh % l: lh % l< 3 l ;(, l< 3 l ;(, l< 3 l ;(, l< 3 l ;(, table 18. input port configuration register 1 - ipcr1 xr82c684 b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ! $+ ! $+ ! $+ ! $+0 $+ $+ $+ $+0 l: lh % l: lh % l: lh % l: lh % l< 3 l ;(, l< 3 l ;(, l< 3 l ;(, l< 3 l ;(, table 19. input port configuration register 2 - ipcr2 $ /$ + , * 1 ( # % * 3( , e ( ( 3 ( * - ( * % * % % 3 please note that the applicable bits, within each of the acr registers, are shaded. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 )2 ' -( d ' ! $+4 $ ! $+ $ ! $+ $ ! $+ $ l l table 4 l l : l l : l l : l l : table 20. acr1- auxiliary control register 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 )2 ' -( d ' ! $+ $ ! $+ $ ! $+ $ ! $+0 $ l l table 4 l l : l l : l l : l l : table 21. acr2 - auxiliary control register 2 ( , $pbq - $pbq note: this ?two-tiered? interrupt enabling/disabling approach, for the ?input change of state? interrupt allows tremendous flexibility for the user. setting or clearing the bits in acr1[3:0] and/or acr2[3:0] allows the user to specify exactly which input port pins to be enabled (or disabled) for generating the ?input port change of state? interrupt. setting or clearing imr1[7] and/or imr2[7] allows the user to ?globally? enable or disable this interrupt. ( * 3 $+% 3( ( (' 3 (' * (, ( ( % " ( ' / , * 1 3 ( * ' $+ ' ( % % % * % ( ( % * # 3 ( , * $+%# ( % % / , * 1 ( # + 3( ( 7 ( ( % ,, *( % * ' ,( , ( ( e.3 44 pin plcc packaged quarts @@ ( +< '6, % ' 3( & * ( ( %# $+# $+# $+0 $+ * # & ( * '( % ( (' ( % ( ( % * '( % * ' ' 5" ' '6 ( % ( ( @@ ( +< '6, ( f. output port ' %(%% * . ( + + ' % % , % ' % * (( , %% %(, % & ( & , ( , * ,(% % # )# # ! # )# # ! % ' *(, ( ,(% %# + + e % %% %(, % + ( % xr82c684 b ( # 3 (' 3% ( % ( 3( ( %' + , ( , + (% ( (** * ' ( 3 ( % &(' % + '( '( & ' %(%% * 3 + ,(% % + +# . ( % % % + ' % + ( % + +b + ' % + ( % +0 +9 ' % * +% ' % * ' % * + ( % " # (* ( +p9q (% % ,(' /1# (% 3( % ( +9 + ( ( , ,(' /1 <(6 3(% # (* ( +p9q (% % ,(' /1# (% % % ( +9 + ( ( , ,(' /1 ( , 6 % , ( , ( (% ' % % '' (% (% * e 3 (( , (% # % ( 6 * * %% (,, ' %7 + )(% d# + )(% d# + )(% d + )(% d + )(% d + )(% d ' % ( % + + ( % + +b (( &# + )(% d + )(% d ' % ( % + + ( % +0 +9 $ (% ( 3 ( 6( , ( / + )(%1 ' # % (% % ( , (% ,(' /1 ( ( + ; 3 # (% '( % % ( % ( , ' % ( , + ( % ,(' /1f ' & ( % ( 3 % * + ( % (% ( + <(6 3(% # 3 ( + )(% ' (% ( 6 # % '(*( (%# 3( ( ' % ( , + /' 1 ,(' /1 ; 3 # ' % ( , + ( % % ,(' /1 % % * ' ( 3( ( * +%# * 3( , + 3 % +# (% 11 * # % * ' + ( # * 3( , + (% ,(' /1 (% * + ' % ' ( (( & ( (% % & %% (,, / + )(% 1 ' % table 1 3( '' &( , # ! )%# % '(*&( , (%# 3( ( +# % l % # l ' , ( (% ' & %% (,, u + )(% 1 ' % table 1 3( '' &( , # ! )%# % '(*&( , (% % l ' # l ' , f.1 writing data to the oprs/output port pins % ( ( # % * +% ' % i &# + ( % (% ' & * / %% (,, 1 ' % + )(% d + )(% d + )(% d + )(% d ' ** ' * %( , % ' % (%'%% 3 f.1.1 set output port bits command ' ' % ( 6 /5 + + )$ d1 ' (% % % 3 (( , ' % ! )% !b ! %% 5 . * +b + & /1 "(%% 3( ( ' ' % * ! )%# ' % ( , (# 3( ( + (% % ,(' / (, 1 & /1 (% % % (% 3 ( %% 5 . # % * ' % ( , (# 3( ( + (% ' , e ' % (% 3& %7 & /1 (% % ! )%# ( , % * / + )(% d1 ' # ' % ( , + ( (% % ,(' / 31 * & /1 (% % ! )%# ( , (% ' # % * ' % ( , + ( (% ' , for example % ' * + +pb7q l p# # # # # # # q ; ' # % * + ( % % * 3%7 p+b# +.# +9# +@# +4# +# +# +q l p# # # # # # # q $* 3 3 ( * 3( , %% 5 . f p!b##!q l p# # # # # # # qf % ( , % * + ,(% )(% * 3%7 +pb7q l p# # # # # # # q % i &# % * + ( % % * 3%7 p+b# +.# +9# +@# +4# +# +# +q l p# # # # # # # q xr82c684 b4 figure 38. illustration of the ?set output port bit #1? command and its effect on the output port register and the state of the output port pins * + +( % +b + $ (( +pb7q ( +pb7q ! )%# !b ! ! %% 5 00001111 1111 1111 11111111 0000 0000 00000000 (% " * / + )(% d1 ' (% ( % ( figure 38 $ % &# * / + )(% d1 ' f ! l f % % ( ' , * +p q# + ( + ! l f % % ( +p q l /1# + ( # + l /1 / + )(% d1 ' (% & %(( / + )(% d1 ' "' % 3 3 ( %% 5 figure 38a % % ( % ( * / + )(% d1 ' (% ** ' + ,(% % * + ( % figure 38a, illustration of the ?set output port bit #2? command and its effect on the output port register and the state of the output port pins. * + +( % +9 +0 $ (( +pb7q ( +pb7q ! %% 0000 0000 0000 00000000 1111 1111 1111 11111111 ! )%# !b ! xr82c684 b@ $ % &# * / + )(% d1 ' f ! l f % % ( ' , * +p q# + ( + n0 ! l f % % ( +p q l /1# + ( # + n0 l /1 f.1.2 clear output port bits command ' * ( 6( , (% ' (% & %(( * / + )(% :!%1f "' ( % 3 3 ( % %% * ( % p+b##+q %% * ( % p+9# # +0q & /1 (% /3 ( 1 (% %%# ' % ( , ( ( + ,(% (% % ,(' / 31 ' % ( , + ( (% % ,(' / (, 1 & /1 (% 3 ( (% %%# % * ' % ( , + ,(% (# ( % * + ( (% ' , " % ' % * + ,(% # + l p# # # # # # # q % i &# % * + ( % 7 p+b# +.# +9# +@# +4# +# +# +q l p# # # # # # # q $* 3 3 3 ( p!b##!q l p# # # # # # # q %% # % ( , ' % * + ,(% 3( 7 +pb7q l p# # # # # # # q # % ( , % * + ( % 3( 7 p+b# +.# +9# +@# +4# +# +# +q l p# # # # # # # q (% " * / + )(% d 1 ' (% ( % ( figure 39 figure 39. illustration of the ?clear output port bit #1? command and its effect on the output port register 1 and the state of the output port pins * + +( % +b + $ (( +pb7q ( +pb7q ! )%# !b ! ! %% 5 0000 1111 1111 1111 1111 0000 0000 0000 1111 0000 $ % &# * / + )(%1 ' f ! l # % % ( ' , * +p q ' , ( % * + ( # + ! l # % % ( +p q l # % % ' % ( , + ( # + # ,(' /1 / + )(% d1 ' (% & %(( / + )(% d1 ' "' % 3 3 ( %% figure 39a % % ( % ( * / + )(% d1 ' (% ** ' + ,(% % * + ( % xr82c684 b9 * + +( % +9 +0 $ (( +pb7q ( +pb7q ! %% 0000 0000 0000 0000 1111 1111 1111 figure 39a. illustration of the ?clear output port bit #2? command and its effect on output port register 2 and the state of the output port pins 1111 0000 ! )%# !b ! 1111 f.2 output port configuration registers (opcr1 and opcr2) + ( % ' % % 2 + % ( %# & ' ' *(, % ( * '( % table 22 (%% '( % * ' * + ( % output port alternate function(s) + -rtsa: i % * : 7 (% (% '( < 3 * * '( + -rtsb: i % * ) : 7 (% (% '( < 3 * * '( + txca_16x output: .8 %( '6 7 txca_1x output: 8 %( '6 rxca_1x: output: 8 ' ( '6 +4 txcb_1x output: ) 8 %( '6 7 rxcb_1x output: ) 8 ' ( '6 c/t1_rdy: -( & * - d : 7 (% (% ! ( 3 % % -( & +@ rxrdy/-ffull_a output: ' ( &- $ $ (' : 7 (% (% ! ( # '( 3 * 8!h- << g * '( +9 rxrdy/-ffull_b output: ) ' ( &- $ $ (' : 7 (% (% ! ( # '( 3 * 8!h- << g ) * '( +. -txrdy_a output: %( & $ (' (% (% ! ( # '( 3 * 8!h g * '( +b -txrdy_b output: ) %( & $ (' (% (% ! ( # '( 3 * 8!h g ) * '( +0 -rtsc: i % * note: this output is an open-drain, active low signal for the rts function. + -rtsd 7 i % * ! note: this output is an open-drain, active low signal for the rts function. xr82c684 b. output port alternate function(s) + txcc_1x: 8 %( '6 txcc_16x: .8 %( '6 7 rxcc_1x: ) 8 ' ( '6 + txcd_1x: ! 8 %( '6 rxcd_1x: ) 8 ' ( '6 c/t2_rdy: -( & * - d note: this output is an open-drain output when used as the counter/timer ready output. + rxrdy/-ffull_c: ' ( &- $ $ (' note: this is an open-drain, active-low output for the rxrdy/ffull_c function. +4 rxrdy/-ffull_d: ' ( &- $ $ (' note: this is an open-drain, active-low output for the rxrdy/ffull_d function. +@ -txrdy_c: %( & $ (' (% (% ! ( # '( 3 * 8!h g * '( +9 -txrdy_d: ! %( & $ (' (% (% ! ( # '( 3 * 8!h g ! * '( note: the ?shaded? output port pin alternate functions are only available in the 68 pin plcc package option. table 22. listing of the alternate functions for the output port & * '( % * ( % + ( % % ' & 3 (( , ( +% ( * * % 3 ,(% % * 3% bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 op7 op6 op5 op4 op3 op2 l +pbq l 8!h) l +p.q l 8!h l +p9q l 8!h- <<) l +p@q l 8!h- << l +p4q l - d l 8) 8 l 8) 8 l +pq l 8 .8 l 8 8 l 8 8 table 23. output port configuration register 1 - opcr1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 op15 op14 op13 op12 op11 op10 l +pbq l 8!h! l +p.q l 8!h l +p9q l 8!h- < xr82c684 bb f.3 44 pin plcc packaged quarts @@ ( +< '6, (' % & * %# +# +# +0 + ; ' ** ' * / + )(%1 / + )(%1 ' % & ** '% % * ( % (( &# + ,(% % ** ' * ' * @@ ( '6, # %( ' % ,(% % 3 % % '(*& * '( % * + ( % + +b# + +9 ; ' # # )# ! & ( ( * '( % ( (% %( * 80.0@ g. serial channels a, b, c and d 5' % ( ' * ' (% % * " %& ' % ' ( %( * ' % ' ( & % ' ( ( , * i '& * )2# -d -d# " ' '6 % 3 % ( , ) %( % ( 3 (' ' ( %( * ' ' ( &# ' ' *(, ( ( % ( , %# 3 (' % * * ' (, %('%# % 3 % ( 36 % * ( ('( % $ (% % '( ' ( %& % 3( % ' ( % '% * %( ' ( *( (( * % * % %& % * 3% 8! %( ( ! * 8 %( '6 (, * 8! ' ( ( ! $ * 8 ' ( '6 (, * (% % '( * % (%'%% % % ' % ( ' ' % % ' % (% 37 %( %( ; ( , ,(% %( (* ,(% ' ( ' ( ; ( , ,(% ' ( (* ,(% % ,(% ,(% % ,(% section b.2 # ! ' ( , '6 ' ,(% section d # (( , ) '6 g.1 transmitter (tsr and thr) %( '' % * + ' % ( % ( ( % 3 ( (% 8! ( # ( , % # % ( (& (% % i( & %& ' % ' 5' %( ' %(%% * %( (* ,(% %( ; ( , ,(% ; ; (% ' & 4 & $ figure 40 % % %( (*( ( % ( * ; + ( (( % %(%%( * % ( & 3 (( , ' ' ; ' ' 3( ( ' %% , $ # ( ( ' % ! ( , %(( * ; # ' ' (% % ( (j (% %( * ' ( ( 8! ( xr82c684 b0 8! , ( , ( ! %( ; ( , ,(% %( (* ,(% %( '6 * (( , ) '6 8 ! )%7 + ! * + figure 40. a simplified drawing depicting the transmit shift register and the transmit holding register e %( (% ( ( '( # 8! * (' ' 3( ' ( % & 6( , ,(' / (, 1 ; 3 # c% ( %(%%( * ' ' # %( % ' ( & , ( , /1 ( ( (% %(' & 8! ,, ( , / 31 * ( ( # * 3( , ( ( + ( * ' ( , ' ' $ ( & * %(%%( * (# % %(, (*(' ( * ' ' 3( % *( %# * 3 & , %%( & %(, (*(' (% $* ' ('( ' ' % * (# %( 3( % / (&1 ( 3 % %(, (*(' ( * ' ' + ( figure 41 % % 3 * * * %( 8! $ (% '% # %( (% % 9! . # 3( 0 : ' 0 (% ' ' # : (&# )( )( )( %( $ )( 8! figure 41. the output waveform of the transmitter while sending 5d (8-n-1 protocol) ' , , $ i % + & % ( , $pq# $p@q# $pq $p@q * % # )# # ! % '( & $ (% '% # 3 , $ i % &( %( ; & * ' ' % + ' % (' (% ( i % & 3 (( , ' ' & ; xr82c684 b %( ' (% ( ,(% % section b.2 $* ' (% (%% (% %( # 3 ( %( ' ' % ( ; # %( 3( ' ( %(( , * ( ( , 3( ( ; # ( & ' & & * ' ' % : 3 ' ' % ' 3 ( ; ' /!(% %( 1 ' % (%% g.2 receiver (rsr and rhr) * '( * % ( ' ( (% ' ( % ( 8! ( f ' ( # 3 ( ' & + ' ( (% % % %( * ' ( , ' '6( , (&# (* (& (% ( , % ' ( ' %(%% * ' ( (* ,(% ' ( ; ( , ,(% ; ; (%# ( %% ' # & $ ' ( ' ( % 8! ( # 3 ( (% % ( & % (* , * 3 %# (% ' * # (% %* ; (% ' ' (% ' %% , 4 & % * $ ' ' ( ' ' ' % * $ # ( ' / 1 & + f 3 ( % ; figure 42 ('% %( (*( 3( , * ' ( ' ( (* ,(% 8! $ ' ( , ( ! ' ( ; ( , ,(% ' ( '6 * (( , ) '6 8 ! )% & + figure 42. a simplified drawing of the receiver shift register and receiver holding register ' ( * '( % & % %( , , 8! ( e * %( (% ( # (% 8! ' % i &# 8! ( (% ' ( % & / 6( ,1 ! ( , (% ( ' ( (% ( '( (% ' (( , ' %%( , & ; 3 # 3 * %( % % (# 3( (% 8! ,, ( , / 31# ' ( ' '6# 3 (' (% . ( % 3( ." ' '6# 3( % % ( , (% ( $* ' ( ( % (% 8! ( (% %( / 31 * (% b % # ' ( 3 ' %( % (% %(, ( ( $* 8! ( (% / 31 b % # ' ( 3( (, (% 3 3 % % / (% 1 (% b % # ' ( 3( % ' %'' %%( ( ( ( ( % - 3( " ' '6 % * (% ." '6 (% 3 * (*& ' / 31 ( 8! ( (% ( ( % (% % ( % ( 3 " ( % ( , ' '6# ( ' ( , % ( % ( (% % ' ( ( ( * (% ( ( please note that if a 16x clock is selected for the receiver, this over-sampling procedure occurs with each and every start bit. xr82c684 0 ' ( 3( ' ( % ' ( ' ( * ' ' * 3% (# ( ( ( % ' ( * ' ' k% ) ' ( 3( ' '6 (& (* , 3( % * + ( $* ' ( % % 6 ' (( (% ( (& ' '6 (* & 3% (f %'' %%* ' ( * ' ' (% % f ' ( 3( % % % '' ' * ( * " ' ' receiver errors $* ' ( % % / 61# % ( * + (# ( , 5 5 (% * ,, & % ( ,# p.q l $*# ' ' ( * ' ' # % % i (& ' '6 (% ( ' '# + (& 5 +5 (% * ,, & % ( , p9q l $* ; 3% * # ' ' "(% ( f (* % ( ' % ( , 8! ( f ' ' ( 3( 3 ( # ' ( 5 5 ' (( 3( * ,, ( % ,(% p@q l (% ( % & % % ( %% * ( & (* 8! ( (% %' ' (( * ( ' ' ( # + ( 3% ' + ( % ( , % ( %' f ' ( ) 6 ) ' (( (% % e (% ' (( (% ' % ( ,% / ' ( ) 61 ' (( (% * ,, ( % ,(% pbq l /) 61 ' ' (% ( ; ; 3 # * (% ' ( ( ; ( 8! ( % / 61 ' (( 4 ' % ( , /! ) 61 ( (% i % (* , * ,, ( $ % ,(% ' 8! ( % / 61 ' (( # % % i ' ' % 3( ( ;# ' % ( , /! ) 61 ( ' (( 3( ' ,( i % (* , * ,, ( $ % ,(% ' , , $ i % + (* 8!h ' ( & << $ (( "(%% 3( ( & * * ' % 8!h (( "(%% 3 % ' ' * "(%% 3( ( ;# (% ( & 3(( , / 1 & + << ' (( "(%% 3 ; (% ' & * ' '' & 3 ' ' % * ( + % / 1 $ % ' % ' $ i % '' ( 8!h << ' (( ( ,(% % % ( % & % ( , $pq# $p9q# $pq $p9q * % # )# # ! % '( & 5' ' (% i( 3( % ,(% % % ( ' ( ( , * % ' % * % ,(% % 3 (%'%% ( ( % '( % * % ; 3 # ( (%'%%( * ( * % ,(% % % 3 g.3 mode registers, mr1n and mr2n ,(% %# 3 % % '(*& * ' % -% 3(% ' % ,(% % % 3 % ' *(, ' % ,, ( % 6( , ' (i % (% * ' * % ,(% % (%'%% 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx rts control rx interrupt select error mode parity mode select parityselect number of bits per character l: lh % l"!h l << l ' l ) '6 l e( + (& l ' + (& l : + (& l ( ! l 5 l l 9 l . l b l 0 table 25. mode registers - mr1a, mr1b, mr1c, mr1d * ' ' (% '' %% 3 ' k% ( ( % ( (% % & 3 % & / % + ( 1 ' ( 6 ( ' k% ' ,(% * & 3 ( # ( 3( (' & ( xr82c684 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 channel mode tx rts control cts enable tx stop bit length l : l 5' l < ' < l < l: lh % l: lh % l 9.4 l .9 l .00 4 l b9 @ l 04 9 l 0b9 . l 40 b l 0 l 9.4 l .9 l .00 ) l b9 l 04 ! l 0b9 5 l 40 l table 26. mode registers - mr2a, mr2b, mr2c, mr2d mr1n[7] - receiver request to send control ( ( &# i % (% %% , & ( 6( , / + )(% 1 / + )(% 1 ( ( ; 3 # (* pbq l (% % # ' ( 3( ' ,( * '(*(' &# % ( , (% ( 3( 3 ' ( , (* (% ; (% * (% /* 3 ' 1 ' (i (% % * ( ( , ' ( 5 % figure 42 % % (, 3 (' ( % % 3 ' ( i % ' *(, ( 3 * '( mr1n[6] - receiver interrupt select (% ( % '% ( 8!h %% ( << %% ( * ' % % ' ( ( * , ( , $ i % + # % ( , * 3( , $ % ,(% (%7 $pq# $p9q# $pq# $p9q * % # )# !# % '( & mr1n[5] - error mode select (% ( ' % ( * $ %% (% +5# 5# ' ( ) 6 * $* (% ( (% % /1# (% (' ' 3( ( / ' 1 5 $* (% (% (% % /1# (% (' ' 3( ( /) '61 5 $ ' ' % %% (% & & ' ' (% ' & * $ $ '6 # % (% % ' ( ,(' * %% * ' ' % ' ( , * $ %( ' % / % 5 %1 ' * 3% (%% mr1n[4:3] - parity mode select $* /3( (&1 /* ' (&1 ( (% , # (& ( (% %( ' ' % ' ( * % (& ' '6 ' ( ' ' % section h.2 * %' (( * ( ! ( mr1n[2] - parity type select (% ( % '% !! 5>5: (& (* /e( + (& 1 (% , % * * ' (& ( (* / ' + (&1 (% , $ ( ! ( % '% % * -! * , ( (% ( % ** ' (* /: + (&1 (% % ' ( p@74q mr1n[1:0] - bits per character select '% * (% %( ' ( ( *( * ' ' (% % ( ' # +$h# + (% mode register 2 (channels a, b, c and d) * ' (% '' %% 3 k% + ( ( % # 3 (' '' % * & '' %% k% ,(% % i / %1 /3 ( %1 % ' , ' % * ( mr2n[7:6] - channel mode select 5' ' ( * * % ( , pb7.q l ' *(, % ' ( : $ (% # xr82c684 0 ' ( %( ( & figure 42 % % (, ('( , : ( ( , pb7.q l ' % ' ( (' 5' # 3 (' (' & % (% ' ( figure 44 % % ( , ('( , (' 5' ( * 3( , ' (( % & 3 ( ( (% figure 43. a block diagram depicting normal mode operation 8! $ ' ( , ( ! ' ( ; ( , ,(% 8 ' ( (* ,(% ! )% & + %( (* ,(% %( ; ( , ,(% 8 8! , ( , ( ! 0 0 ! )% + * + xr82c684 04 figure 44. a block diagram depict automatic echo mode 8! $ ' ( , ( ! ' ( ; ( , ,(% 8 ' ( (* ,(% ! )% & + %( (* ,(% %( ; ( , ,(% 8 8! , ( , ( ! 0 + ;% : '' %% %( ' ( (% %( ' k% 8! ' ( % %( 4 ' k% 8!h 85 %% (% ( '( @ ' ( (& (% ' '6 (% , * %(%%( %# %( (& (% % ' ( 9 ' * ( , (% ' '6 % (% %( % ' ( . ' ( 6 (% ' % ' ( ( " ( % ( (% ' b + ' ( ' ('( % % &# + %( ( 6 (% (% 5' ' ' ' *(, ( * 3 (, %(' % local loopback mode (% (% % ' & % ( , pb7.q l figure 45 (% (, ('( , < ' < '6 ( xr82c684 0@ figure 45. a block diagram depicting local loopback mode operation 8! ' ( ; ( , ,(% ' ( (* ,(% ! )% & + %( (* ,(% %( ; ( , ,(% 8 0 0 ! )% + * + 8! > $ (% 7 %( (% ( & ' ' ' ( ( %( ' '6 (% % * ' ( 4 ' k% 8! (% 6( , (, @ ' k% 8! ( (% (, 9 %( (% # ' ( . + %( ' ( ' ('( % ' ( & xr82c684 09 remote loopback mode (% (% % ' & % ( , pb7.q l figure 46 % % (, ('( , < '6 ( $ ' ( , ( ! 8! ' ( ; ( , ,(% ' ( (* ,(% %( (* ,(% %( ; ( , ,(% , ( , ( ! 8 8 8! note: the cpu has no access ot the serial data during remote loopback mode. figure 46. a block diagram depicting remote loopback mode $ (% f ' ( (% %( ' k% 8! ' ( (% % + %% ' (( % ' '6 4 + (& * ( , % (% %( % ' ( @ ' ( % 9 ' ( 6 (% ' % ' ( ( " ( % ( (% ' mr2n[5] - transmitter request-to-send control ( ( &# i % (% %% , & ( 6( , / + )(% 1 / + )(% 1 ( ( # & %&% % *3 ; 3 # % ( , p9q l 3% %( , (' &# ( ( * ' ' % ( ; %( 3 & figure 49 % % (, ( % 3 %( i % ' *(, ( 3 * '( mr2n[4] - clear to send control $* (% ( (% # ' % ( $+ * # $+ * )# $+0 * # $+ * ! % ** ' %( $* ( (% /1# %( 3( ' '6 % * (% ( ' ( (% ( & % ' ' $* (% 3 / 1# ' ' (% %( $* (% (, , # 8! ( % ( 6( , % %(%%( * " ' ' (% & ( , % 3 , % ( ( 3 ( ' ' (% ( , % ( (j ** ' %(%%( * ' ' (% (% * ( % ( figure 47 figure 49 mr2n[3:0] - stop bit length (% ( *( , % ( * % (% ' %( ' ' ( ( * -. ( ( -. ( ( %# ( ( ' % * -. (% ' , * ' ' , % * .# b 0 (% 9 ( ' ' # % ( ( ' , * -. ( ( % $* " " ' '6 (% , * %( ' '6 8 # p4q l % '% % ( ( * ( ( p4q l % '% ( * 3 ( ( % * %(%%( xr82c684 0. ' ( & ' '6% * 6 ' (( ' * *( % % ( (%# ( ( * % (& ( (% % , %% * , %( % ( , $* ' ( % % / 61 / 5 1 5 (% * ,, ( % ,(% g.4 status register, srn ' % ,(% ( % % 3( %% ; ; ' ( %( $ %# % '( &f % % ( + 3( % * i (& * ' ( * & ' ( $ % ( (' % % * ( %&% % 3% + ' '6 % (* %( (% & - (% & * * + $ % ( (' % % ( (' 3 ; % ' ' # 3 (' (% 3(( , & + # (% * ( ' * ' (( , & ' ' % 3( %( ' ( $ %% ( (' % ' ( 3 ( * % ,(% ( * % ,(% % % * & ' ( % ( * * % ,(% (%'%%( * ' ( * 3%7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 received break framing error parity error overrun error txemt txrdy ffull rxrdy l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % table 27. status register - sra, srb, src, srd srn[7] received break (% ( ( (' % j ' ' * , ' ' , 3% ' ( 3( % ( & %( , $ %(( (% ''( 3 6 (% ' ( (( %* % ( $ ( ( ( ( 8! ( % 6( , % * % * ( ( (% (% *( % 3 %'' %%( , % * ( " " ' '6 e (% ( (% % # ' k% / , $ ) 6 %1 ( ( $ (% % ( ( $ (% % % 3 * 6 ' (( # % *( # (% ' ' (k% 6 ' ,(' ' ' 6% ,( ( ( * ' ' ; 3 # 6 % %(% ( * " ' ' ( ( * ( ' $* 5 # * ' # % % / ' 1 # (% ( & ( % ' * ; (% ( 3( ' (* 8! ( (% , ,(' / (, 1 # ( " ' ' $* /5 1 % % /) '61 # (% (# ' % 3( ( %% ( / % 5 %1 ' % ( 6 % % table 2 + % (* 5 (% /) '61 (% (# ( % ,(% 3( ( % # * % % i ' ' %# ( * ' (( * % ' ( ' ' %# ( / % 5 %1 ' % ( 6 srn[6] framing error 3( , ' ( * ' ' (%# & %% '( (& (# ' ( 3( ' '6 * / 61 ' (( ( ( * 3( , % (& ( (% / 61 ' (( (% + ( $* ' ( % ' / 61 (% ( # ( (% ,, / (, 1 * ,,( , '' ' * 5 5 $* 5 % % / ' 1 # (% ( & ( % ' * ; $* (% ( (% % * ,( ' ' # ( 3( ' (* + ( (% & ' ( " ' ' $* /5 1 % % /) '61 # (% (# ' % 3( ( %% ( / % 5 %1 ' % ( 6 % % table 2 + % (* 5 (% /) '61 (% (# ( % ,(% 3( ( % # * % % i ' ' %# ( * ' (( * % ' ( ' ' %# ( / % 5 %1 ' % ( 6 srn[5] parity error (% ( (% % 3 /e( + (&1 / ' + (&1 % , (* ' % ( , ' ' ( $ 3% ' ( 3( ( ' ' (& xr82c684 0b $* 5 % % / ' 1 # (% ( & ( % ' * ; $* (% ( (% % * ,( ' ' # ( 3( ' (* ' ( (& (% ' ' ( " ' ' $* /5 1 % % /) '61 # (% (# ' % 3( ( %% ( / % 5 %1 ' % ( 6 % % table 2 + % (* 5 (% /) '61 (% (# ( % ,(% 3( ( % # * % % i ' ' %# ( * ' (( * % ' ( ' ' %# ( /55 5 1 ' % ( 6 srn[4] overrun error $* % # (% ( ( (' % ' ' % ( ' ( %# ( (% % ' ( * 3 ' ' 3 $ (% * ' ' (% & ( 3(( , * & $ %(( e (% '' %# ' ' ( (% 3 ( + % (6 % ,(% (% * 5 ( , 5 # +5 + (& 5 ) ' ( ) 6# 5 5 ( (' (% 3&% * ,, /) '61 5 %(% 5 ' (( (% * ,, ' ' ' ' %(%# & ' 3 / % 5 %1 ' (% ( 6 srn[3] transmitter empty (txemt) (% ( (% % 3 %( % $ (% % * %(%%( * % % ( * ' ' (* (% ' ' ( ; 3(( , %(%%( (% ( (% ' 3 %( (% (% # 3 + 3 ( % 3 ' ' ; srn[2] transmitter ready (txrdy) (% (# 3 % # ( (' % ; (% & & '' ' ' * + ( (% ' 3 + 3 ( % 3 ' ' ;# (% % 3 ' ' (% %* 8!h (% % 3 %( (% ( (( & (% % 3 %( (% (% ' % ( ; 3 ( %( (% (% 3( %( srn[1] fifo full (ffull) (% ( (% % 3 ' ' (% %* * ; %* '% % ( ' * # ( # $ %(( % ''( $ (% % 3 + % ; $* ' ' (% 3(( , ( '% $ (% * # << 3( % 3 + % ; srn[0] receiver ready (rxrdy) (% ( ( (' % % ' ' % ' ( (% 3(( , ( $ & + $ (% % 3 ' ' (% %* * ; (% ' 3( + % % ' ' ' & % ( $ + % % * ' (( % * ,, & % ,(% ' % , , $ i % + ; 3 # % ' (( % * ,, & % ,(% ' , , $ % ' (( % (% 37 p.q ( , 5 p9q + (& 5 p@q 5 * # (* %&% ' '6( , (% & # % (% ' ( ' ' ' & ' '6( , % ,(% h. special modes of operation h.1 rts/cts handshaking ' , % - ; % 6( ,# % % * * 3 ' 3( (' % (% % '( 3( %' ( ' * ( % 3% % ( ( ( , - ; % 6( , '(*(' &# % ( % 7 ' ( - ; % 6( , %( - ; % 6( , h.1.1 receiver-controlled rts/cts handshaking $ (% # ' ( % ( (& (' & , %(( , (' '(*(' &# (% 3% ' ( , %(, (* (% ; (% * f # (% &# & ** '( ( ( , ' ( 5 % figure 47 % % (, * " ( % ( , ( * ' ( ' *(, ( xr82c684 00 figure 47. block diagram and timing sequence of two quarts connected in the receiver-rts controlled configuration 8! 8!) ' (( , ! (' %(( , ! (' 8! 8!) + ) $+ $+ << + << 8! +@ ) + figure 47 % 3% 3 (' %# / ' (( , ! (' 1 / %(( , ! (' 1 % (' % %' '% * ( ( (% " %* * 3 (% " (% , ( , (, # * ( ( ,# *' / ' (( , ! (' 1 % %( / %(( , ! (' 1 % ' ( # (% " # (% %( , * / ' (( , ! (' 1 ) * / %(( , ! (' 1 " % % 3( %%( / ' (( , ! (' 1 % , %' pbq l '' ( , section g.3 # (% % % ( , ( , / ' (( , ! (' 1 * ' ( (( &# / %(( , ! (' 1 % , %' )p@q l '' ( , section g.3 # %( * ) * / %(( , ! (' 1 % 3 , ) ( ' $ (% " # / ' (( , ! (' 1 ' % %(, (% %(, (% * ( ' & ( ) ( * %(( , ! (' $* ; * / ' (( , ! (' 1 (% * % (' & << ( , ,(' / (, 1# 3( (' & , & ( * ' ( * % % i &# ) %( * / %(( , ! (' 1 3( (% ) ( , 3( ( %( & 8! * / ' (( , ! (' 1 $* + % / %1 ; * ' (( , ! (' # ; 3( , * # << ( (' 3( ,, * % $ (% '% # << ( (' (% ' ' % ( * + $ % % << ,, ( , * % # + 3 ( (% / ,( , 1 * << % $ i % + 3 % (' (% /$ 1 & /3 (( ,1 p!b##!q l p# # # # # # # q %% 5 (% '( " ' % / + )(% d :!1 '% % +pq ,, / (, 1 + ( + ,, / 31 % i &# (% 3 %% e( * / ' (( , ! (' 1 ( , %% ( * / %(( , ! (' 1 (% xr82c684 0 3 %% # % 3 %(%%( * / %(( , ! (' 1 / ' (( , ! (' 1 (% 3 ( figure 47 % 3% 8! ( ' (( , * % %% ; 3 # ( (% " # (% 3 & ' ( ' ' 3 '% % ; * / ' (( , ! (' 1 * << ( (' %% (% 3 %% * / ' (( , ! (' 1 (% 3 (' & , ( ' ( ' %(, * # %(%%( * ) * %(( , ! (' (%# ' ,( # ( ( ( figure 48 % % * 3 (, ( % ( , , ( ' % ( ( ( , ' ( - ; % 6( , figure 48. a flow diagram depicting an algorithm that could be used to apply the receiver-controlled rts/cts handshaking mode ' (( , ! (' pbq l %(( , ! (' )pbq l %% e ( %% 5 (% ( 6 % /5 + + )$ d :!1 % % + ( # + ,(' /1 $% << %% v : (% (' & : , & ' ( '( h % $% << : , v : h % xr82c684 h.1.2 transmitter-controlled rts/cts handshaking $ (% # %( 3 % ( (& , ' (( , ! (' '(*(' &# (% 3% %( , %(, # ( ( * &( , (% ; figure 49. block diagram and timing sequence of two quarts connected in the transmitter-rts controlled configuration 8!hg 8! + $+ 8! $+ ( +4 8!) %(( , ! (' ' (( , ! (' + 8!hg +. figure 49 % 3% 3 (' %# / %(( , ! (' 1 # / ' (( , ! (' 1 (% " % % 3( %%( / %( ! (' 1 % , %' p9q l # 3 (' % % ( , ( , / %(( , ! (' 1 * %( (% " * %% % / %(( , ! (' 1 % , %' p@q l '' ( , section g.3 # %( * * / %(( , ! (' 1 % 3 , ( ' $ '% * / ' (( , ! (' 1# $+ ( % , , /$ + , * 1 ( i % + *( 3 * $ (' ( % (% 3 ( %' (* $+ ( 3 ' , $+pq l # + 3 /3 ( 1 p!b## !q l p# # # # # # # q %% 5 $ (% % # $ (' ( 3 ( 6 /5 + + )$ d :!1# ( ' %% ,, +p4q ,(' / (, 1 + ( # +4# ,(' / 31 (% 3 # ( # %% ( * xr82c684 / %(( , ! (' 1 3 ( %( / ' (( , ! (' 1 ' %( % ( (% ; * # ( 3( , # ( / %( 1 * e / %(( , ! (' 1 (% ,, / (, 1# $+ ( (% % ,, / (, 1# & , ( , /$ , * 1 ( i % + e( $+pq l # (6 & $ (' ( 3 /e ( 1 p!b## !q l p# # # # # # # q %% $ (% % # $ (' ( 3 ( 6 /<5 + + )$ d :!1# ( ' %% ,, +4 / (, 1 (% 3 ( , ( * / %(( , ! (' 1 ( ( ( %(%%( * * * / %(( , ! (' 1 figure 50 % % 3 !(, 3 (' ('% , ( ' % ( %( - ; % 6( , + % % '6 ( '' ' % 3( ( / ' (( , ! (' 1 e % /e ( 1 '6 ( ( 3( ( / %(( , ! (' 1 $% 85 %% v 5 e ( %% 5 (% (' & : , & ' ( '( + ,, % /;(, 1 $% 8!h : , v 2 /$ + , * 1 $ $+ ( ' (( , ! (' $% $+ l v 22<5 +4 g +$: /<e1 e ( 0 %% 5 22<5 +4 g +$: /;$2;1 e ( 0 %% $:+ $ 55! ! %(%%( (% 3 ( $:+ $ :525! ! %(%%( (% (% : h % h % : h % : figure 50. a flow diagram depicting an algorithm that could be used to realize the transmitter-controlled rts/cts handshaking mode xr82c684 h.2 multi-drop (8051 9 bit) mode. 5' % ( ' * ' ' *(, ( 36 % * * ( ( ' %% ('( % (% % '( 3( *( % % ' ' * ( ! * 3 %# * '( ' * ( , ( ( ! (% (%'%% 3 h.2.1 concept of multi-drop mode (% (% ' ( 3( % ( /:( ( 1 * 09 *( & (' ' % $ (% * ( /% %( 1# ' ' "( * 9. % %( (% %%( # % (' ( figure 51 8! 8! 8! 8! 8! % ! (' ! (' % figure 51. an illustration depicting the concept of multi-drop mode -! <) ) 0 )( ' %%-! )( figure 52. bit format of character data being transmitted in the multi-drop mode /% ( 1 ' (' % / ( %1 & %(( , ' ' &(' & & 3( / %%-!1 ( * , * ' ' (% &(' & % % ( ( (% * ( , %( * & ' ' & # % % ( figure 52 e /% ( 1 3 % %( '6 * * % % %# ( *( % % % %% & ( (*( % / , 1 %% & (** % * & ( ( ( (% /1 ( %% )& /1 ( ! )& %% )& # 3 # ( % / %1 % ' ' "( ' ( & % (* ( ( (( % (' (% ( , %% ' ( * %% % 3( 3( * ' ( * & % * 3% % % 3 %% 3( % ( ' ( % (% # 3( ' ( (, & % * 3% & 3( ( ,( 3 " %% & (% %( & /% ! (' 1 h.2.2 quart multi-drop operation ,( ' # 3( ( (% , ( ( ! & % ( , p@74q l /# 1 $ (% # %( ' ' ' %(%% * (# , * (%# %%-! -! * , (f , + ( , -! l ( (' % ' ' (% # 3 ( -! l ( (*( % ( % %% transmitter operation during multi-drop mode % -+ ' % % * %( ' ' & , ( , pq * ' ( ( , (% ( ; ( , pq l /1 % % ( -! l /1 % ( , pq l /1 % % ( -! l /1 figure 53 % % ' * 3 (, * %(( , ' ' % %% !# 3 ( ( ( ! xr82c684 4 $ 6 /55 +$:51 ' e ( " ( ,(% -! )( /1 e ( """"""" ,(% %( %% ' ! (' e ( ' ; -! )( /1 e ( """"""" ,(% %( ! ' ! (' e ( ' ; ! ' % e ( '( ! (' : h % $ 6 /55 +$:51 ' e ( " ( ,(% figure 53. a flow diagram depicting a procedure that can be used to transmit characters in the multi-drop mode receiver operation during multi-drop mode e ' % , ( ( ! # ' ( % (% &(' ' *(, ( # ' ( 3( ' ' ( ; % 8!h ( (' - ( (* -! ( (% /1 %% * , ; 3 # ' ' 3( (%' (* (% -! ( (% /1 ! * , * # ( % % 8!h ( (' # + % ' ( ' ' ( (* %% ( % % ' % * + $* %% % ' # ( ('( , ( (% , # + % ' ( # ( ( * % % i '6% * ' ' ( % ' ( ( ! 3( ' %% % ( : ( ' ( ' ' % '' %%( + & ( , ; % * -! * , ( (% ( p9q# % ,(% ( & % ( (' xr82c684 @ /+ (& 5 1 * # ( ' c '( 3( ' ( ' 3 ' ' # + % ' ( ( p9q ( (*& ( (% /1 ! ' ' % ' / , + 1 '% 3 %% ' ' # p9q l/1# ( % ' (% %% 3( (% 3 $* %% % ' # (% + (% ( '(( * " '6 * # 3 % (% ' ( figure 54 % % * 3 (, ('( , ' ' * ( , ' ( ' ' % 3 ( ( ( ! ' ( (% !(% (% ( ( ! p@74q l p# q c ' ' ' ( ( % !(% ( %% ' * ; ;% 8!h $ (' %% v : h % : 5 ' ( e ( " ( ,(% ( ! ' * ; '6 p9q ! % : 3 & ' ( %% ' + %%v $% : 3 ' ! ' p9q l v h % h % : figure 54. a flow diagram depicting a procedure that can be used to receive characters in the multi-drop mode h.3 standby mode & ' ( % & ' % 3 3 (% ( (% i( % # 3( ( /'( ( 1 / & 1 ' (%% ( ' ,(% (% % ' '6% (' "' * ' &% %'( # 3 (' %(, (*(' & ' % ( , ' $ (% & * '( % 3 (' 3( ' ' & ( , ( # 3 (( , / '( 1 ' # % ( 6 ( ,(% # % % (' ( 3( ( 9 % % ( , %( % ' ( % 3 (( , ( * $% $ %6 ,(% % * , ( , ( & (% ' & % ( % ( % * ( , , ' ( % , * / '( 1 ' %( ' ,(% ' % , ( % ( , % & '( ( ' % % ( 3 % xr82c684 9 i. comments about the xr82c684 in 44 pin plcc ' * (% % (%'%% * % 3 (' ( % 3 (' '6, ( .0 ( +< ; 3 # '% * ' * ( % % ( @@ ( '6, * 3( , * % ( (& & " ' '6 %(, % ( (( , ) '6 8-<= ( ( (& ' *(, % + % * '( % 8!h 8!h- << ( (' % j. programming ( * (% , & 3 (( , ' 3 % ( ( ,(% %# 3 ( ( * '6 (% ( & %% ,(% % 3 (' ' & + ,(% %%( , (% % 3 ( table 1 3 % ' % ' % * # $%# $%# +%# +% ,(% % ( (( (j % $>% . ! ( , ( # ' % " '(% (* ' % * ' ,(% % ' , # %( ' ' ( ' , % & % ( ( ( " # ' ,( , * (% ' ' 3 ( (% ( , ' ( & % ( ' ( * % ' ' $ , # ' , % ,(% % 3 (' ' ' ( %( ( % & 3 ( %( ' ( (% # ' ( ' , % % % & 3 -k% % # ' # ' '6 % '# %% ,(% % (' * ' ' ( ( ( no tag % (j % ( %%(, % * ' ,(% bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx rts con- trol rx int select error mode parity mode select parity select number of bits/char. l: lh % l8!h l << l l ) '6 l e( + (& l ' + (& l : + (& l ( ! l 5 l l 9 l . l b l 0 table 28. mode registers 1: mr1a, mr1b, mr1c, mr1d bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 channel mode tx rts control cts enable tx stop bit length l : l 5' l < ' < l < l: lh % l: lh % l 9.4 l .9 l .00 4 l b9 @ l 04 9 l 0b9 . l 40 b l 0 l 9.4 l .9 l .00 ) l b9 l 04 ! l 0b9 5 l 40 l table 29. mode register 2: mr2a, mr2b, mr2c, mr2d bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receiver clock select transmitter clock select table 6 table 6 table 30. clock select registers: csra, csrb, csrc, csrd xr82c684 . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miscellaneous commands enable/disable tx enable/disable rx " ( section b.2 l : , l 5 " l !(% " l : 3 ! : % l : , l 5 " l !(% " l : 3 ! : % table 31. command registers: cra, crb, crc, crd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 received break framing error parity error overrun error txemt txrdy ffull rxrdy l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % table 32. status registers: sra, srb, src, srd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 op7 op6 op5 op4 op3 op2 l+pbq l8!h) l+p.q l8!h l+p9q l8!h- <<) l+p@q l8!h- << l +p4q l - d l 8) 8 l 8) 8 l +pq l 8 .8 l 8 8 l 8 8 table 33. output port configuration register 1: opcr1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 op7 op6 op5 op4 op3 op2 l+pbq l8!h! l+p.q l8!h l+p9q l8!h- < xr82c684 b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 brg set select counter/timer #2 mode and source ! $+ $ ! $+ $ ! $+ $ ! $+0 $ l l table 13 l l: l l: l l: l l: table 36. auxiliary control register 2: acr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 delta ip3 delta ip2 delta ip1 delta ip0 ip3 ip2 ip1 ip0 l: lh % l: lh % l: lh % l: lh % l< 3 l ;(, l< 3 l ;(, l< 3 l ;(, l< 3 l ;(, table 37. input port configuration register 1, ipcr1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 delta ip11 delta ip10 delta ip9 delta ip8 ip11 ip10 ip9 ip8 l: lh % l: lh % l: lh % l: lh % l< 3 l ;(, l< 3 l ;(, l< 3 l ;(, l< 3 l ;(, table 38. input port configuration register 2, ipcr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffullb txrdyb counter #1 ready delta break a rxrdy/ ffulla txrdya l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % table 39. interrupt status register 1, isr1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break d rxrdy/ ffulld txrdyd counter #2 ready delta break c rxrdy/ ffullc txrdyc l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % l: lh % table 40. interrupt status register 2, isr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break b rxrdy/ ffullb txrdyb counter #1 ready delta break a rxrdy/ ffulla txrdya l** l l** l l** l l** l l** l l** l l** l l** l table 41. interrupt mask register 1, imr1 xr82c684 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 input port change delta break d rxrdy/ ffulld txrdyd counter #2 ready delta break c rxrdy/ ffullc txrdyc l** l l** l l** l l** l l** l l** l l** l l** l table 42. interrupt mask register 2, imr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -9 -@ -4 - - - - -0 table 43. counter/timer upper byte register, ctur (applies to ctur1 and ctur2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -b -. -9 -@ -4 - - - table 44. counter/timer lower byte register, ctlr (applies to ctlr1 and ctlr2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $>b $>. $>9 $>@ $>4 $> $> $> table 45. interrupt vector register: ivr (applies to ivr1 and ivr2) k. timing diagrams > 0> % < % > 0> @> figure 55. input and output levels for timing measurements note: ac testing inputs are driven at 0.4v for a logic ?0? and 2.4v for a logic ?1? except for -40 to 85 c and -55 to 125 c, logic ?1? shall be 2.6v. timing measurements are made at 0.8v for a logic ?0? and 2.0v for a logic ?1?. xr82c684 figure 56. reset timing 55 .0 55 00 5 @ e ! !b < : ><$! ><$! < ! !b e ( ><$! ; ; ! e! ! !; !! e! ! e figure 57. xr82c684 read and write cycle timing (88 mode) xr82c684 ! $= $5$ ! !b : > ( > ' $: $5 !$ 5! !$ 5$ !! $ e $; ! % $ figure 58. xr82c684 z mode interrupt cycle timing (88 - mode) xr82c684 9 - e ! !b != ; e e; !! ! !< ! !; ! e 8-<= figure 59. xr82c684 read cycle timing (68 - mode) 9 - e ! !b != e ! !< ; e; e ! !; ! figure 60. xr82c684 write cycle timing (68 - mode) xr82c684 $: != $= 8-<= ! !b >5 !! ! ! !< ! !; ! figure 61. xr82c684 interrupt cycle timing (68 - mode) e ! $+ $+9 + +9 + +; ! : 3 ! +! figure 62. port timing xr82c684 4 ! e $ $ figure 63. interrupt timing <= 8 <= 8 8-<= - <= 8 8 xr82c684 8 8 b4b;j + % &% 7 9 n & s 9 7 9 n & s 9 xr82c684 8 8 4.0.@;j + % &% 7 n & s 9 7 n & s 9 7 7 figure 64. clock timing xr82c684 @ 8 $ 8 8 8! )( ( . '6% 8! figure 65. transmitter timing 8 8 $ 8! 8 8; figure 66. receiver timing xr82c684 9 44 lead plastic leaded chip carrier (plcc) rev. 1.00 d d a a 1 d d 1 d 3 .9 0 @ @9b 49 rrr 9 rrr ) 4 44 94 ) . 4 .. 0 0 4 4 ! .09 .9 b@ b.9 ! .9 .9. .9 ... ! 9 .4 @ . ! 4 9 & b & 9 ) b ) ; @ 9. b @ ; @ @0 b 9 @9 .@ @ symbol min max min max inches millimeters b a 2 b 1 e ( , + d 2 @@ note: the control dimension is the inch column d 3 45 xh2 45 xh1 c r xr82c684 . 68 lead plastic leaded chip carrier (plcc) rev. 1.00 d d d d 1 d 3 d 2 a a 1 .0 .9 @ 90 4 44 rrr 9 rrr ) 4 44 94 ) . 4 .. 0 0 4 4 ! 09 9 9 9b ! 9 90 @4 @44 ! 0 4 . 4. ! 4 0 & 4 & 9 ) b ) ; @ 9. b @ ; @ @0 b 9 @9 .@ @ symbol min max min max inches millimeters b a 2 b 1 e ( , + d 3 note: the control dimension is the inch column 45 xh2 45 xh1 c r xr82c684 b :$5 58 ( % % (, 6 ' , % '% ' ( ( (% ('( ( ( %(, # * ' ( ( (& 58 ( %% % % %( ( (& * % * & '( '(% %' ( ( # ' &% (' % & (, # 6 % % ( '( '(% * * ( * ( , % %' % ' ( ( & * ( % ( % % & & ( , % k% % '(*(' ('( e ( ( * ( ( (% ('( % ' * & ' '6 f % %( ( (&# 3 # (% %% * ( '' '( % 58 ( % ' % * & * (% '% ( (* % ('( % 3 *( * '( * ' ' % & " ' '% *( * (* % %&% %(, (*(' & ** ' (% %* & ** '( %% + '% (j * % ( %' ('( % %% 58 ( ' ( %# ( 3 (( ,# %% ' % (% %(%*'( 7 (%6 * ( c & , % ( ((j f % %% % %' (%6%f ' ( ( ( (& * 58 ( (% i & ' '( ' % ' % & (, 58 ( !% '( # ( 3 # 3( ( 3 ( ' % * 58 ( (% ( ( |
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